公开(公告)号：US10482943B2

公开(公告)日：2019-11-19

申请号：US15636565

申请日：2017-06-28

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter Chun ,  Yanru Li

IPC: G11C7/00 ,  G11C11/406 ,  H01L27/108 ,  H03M13/09 ,  H03M13/11

Abstract: Systems and methods are disclosed for error correction control (ECC) for a refreshable memory device coupled to a system on a chip SoC. The memory device including a parity region and a user data region. A method includes determining with the SoC a first refresh rate for the user data region of the memory device and a second refresh rate for the parity region of the memory device, where the second refresh rate is different than the first refresh rate. Parity data is generated for a write operation of a user payload data (UPD) to the user data region of the memory device. The user data region of the memory device is refreshed at the first refresh rate and the parity region is refreshed at the second refresh rate.

公开(公告)号：US10310757B2

公开(公告)日：2019-06-04

申请号：US15684838

申请日：2017-08-23

Applicant: QUALCOMM INCORPORATED

Inventor： Yanru Li ,  Larry Bassel ,  Thomas Zeng ,  Dexter Chun

IPC: G06F3/06

Abstract: Systems, methods, and computer programs are disclosed for reducing memory power consumption. An exemplary method comprises configuring a power saving memory balloon associated with a volatile memory. Memory allocations are steered to the power saving memory balloon. In response to initiating a memory power saving mode, data is migrated from the power saving memory balloon. A power saving feature is executed on the power saving memory balloon while in the memory power saving mode.

公开(公告)号：US09823846B2

公开(公告)日：2017-11-21

申请号：US14464598

申请日：2014-08-20

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter Tamio Chun ,  Suryanarayana China Chittuluri ,  Yanru Li

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/10 ,  G06F12/06 ,  G06F13/16

CPC classification number: G06F3/0607 ,  G06F3/0631 ,  G06F3/0665 ,  G06F3/0683 ,  G06F12/0246 ,  G06F12/06 ,  G06F12/10 ,  G06F13/1684 ,  G06F2212/1048 ,  G06F2212/152 ,  G06F2212/171 ,  G06F2212/206 ,  G06F2212/214 ,  G06F2212/261 ,  G06F2212/654 ,  G06F2212/7201

Abstract: Systems and methods are disclosed for expanding memory for a system on chip (SoC). A memory card is loaded in an expandable memory socket electrically and is coupled to a system on chip (SoC) via an expansion bus. The memory card comprises a first volatile memory device. In response to detecting the memory card, an expanded virtual memory map is configured. The expanded virtual memory map comprises a first virtual memory space associated the first volatile memory device and a second virtual memory space associated with a second volatile memory device electrically coupled to the SoC via a memory bus. One or more peripheral images associated with the second virtual memory space are relocated to a first portion of the first virtual memory space. A second portion of the first virtual memory space is configured as a block device for performing swap operations associated with the second virtual memory space.

公开(公告)号：US09612648B2

公开(公告)日：2017-04-04

申请号：US13962746

申请日：2013-08-08

Applicant: Qualcomm Incorporated

Inventor： Dexter Chun ,  Yanru Li ,  Alex Tu ,  Haw-Jing Lo

IPC: G06F12/00 ,  G06F1/32 ,  G06F12/06 ,  G11C14/00

CPC classification number: G06F1/3275 ,  G06F12/0607 ,  G06F2212/1028 ,  G11C14/0009 ,  Y02D10/13 ,  Y02D10/14

Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method involves configuring a memory address map for two or more memory devices accessed via two or more respective memory channels with an interleaved region and a linear region. The interleaved region comprises an interleaved address space for relatively higher performance use cases. The linear region comprises a linear address space for relatively lower power use cases. Memory requests are received from one or more clients. The memory requests comprise a preference for power savings or performance. Received memory requests are assigned to the linear region or the interleaved region according to the preference for power savings or performance.

公开(公告)号：US20160307620A1

公开(公告)日：2016-10-20

申请号：US14690204

申请日：2015-04-17

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Jung Pill Kim ,  Yanru Li

IPC: G11C11/406 ,  G11C29/42 ,  G11C29/36 ,  G11C11/4096

CPC classification number: G11C11/40626 ,  G11C7/1006 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C29/36 ,  G11C29/42 ,  G11C29/50016 ,  G11C2207/2245 ,  G11C2211/4062

Abstract: A system and method of refreshing dynamic random access memory (DRAM) are disclosed. A device includes a DRAM, a bus, and a system-on-chip (SOC) coupled via the bus to the DRAM. The SOC is configured to refresh the DRAM at a particular refresh rate based on a temperature of the DRAM and based on calibration data determined based on one or more calibration tests performed while the SOC is coupled to the DRAM.

Abstract translation: 公开了一种刷新动态随机存取存储器（DRAM）的系统和方法。 一种器件包括通过总线耦合到DRAM的DRAM，总线和片上系统（SOC）。 SOC被配置为基于DRAM的温度以基于在SOC耦合到DRAM时执行的一个或多个校准测试确定的校准数据以特定刷新速率刷新DRAM。

公开(公告)号：US20160019158A1

公开(公告)日：2016-01-21

申请号：US14334010

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Subbarao Palacharla ,  Moinul Khan ,  Alain Artieri ,  Kedar Bhole ,  Vinod Chamarty ,  Yanru Li ,  Raghu Sankuratri ,  George Patsilaras ,  Pavan Kumar Thirunagari ,  Andrew Edward Turner ,  Jeong-Ho Woo

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F1/3203 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/50 ,  G06F12/084 ,  G06F12/0864 ,  G06F12/0888 ,  G06F12/0895 ,  G06F17/30902 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/601 ,  G06F2212/6042 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.

Abstract translation: 方面包括计算设备，系统和方法，用于通过集合和方式动态地将系统高速缓存分区到组件高速缓存中。 系统高速缓冲存储器控制器可以管理组件高速缓存并管理对组件高速缓存的访问。 系统高速缓冲存储器控制器可以接收系统高速缓存访​​问请求，并且在系统高速缓存中保留对应于与请求的组件高速缓存标识符相关联的组件高速缓存的位 在系统缓存中预留位置可以激活系统高速缓存中的位置以供请求客户端使用，并且还可以防止其他客户端使用系统高速缓存中的保留位置。 释放系统缓存中的位置可以停用系统缓存中的位置，并允许其他客户端使用它们。 保留系统缓存中的位置的客户端可以改变其在其组件高速缓存中保留的位置的数量。

公开(公告)号：US11636231B2

公开(公告)日：2023-04-25

申请号：US16937907

申请日：2020-07-24

Applicant: QUALCOMM Incorporated ,  Candace Sachi Chun

Inventor： Yanru Li ,  Dexter Tamio Chun

IPC: G06F21/79 ,  G06F11/07 ,  G06F12/14 ,  G06F21/31

Abstract: Various embodiments may include methods and systems for providing secure in-memory device access of a memory device by a system-on-a-chip (SOC). Various methods may include receiving a configuration message from the SOC for configuring a memory access control of the memory device, and configuring the memory access control based on the configuration message. Various embodiments may include receiving an access request message from the SOC requesting access to a memory base address and a memory access range of a memory cell array of the memory device, wherein the access request message includes a read/write operation. Various embodiments may include comparing the access request message with the configured memory access control to determine whether the access request message is allowable. Various embodiments may further include performing the read/write operation in response to determining that the access request message is allowable.

公开(公告)号：US11631450B2

公开(公告)日：2023-04-18

申请号：US17377799

申请日：2021-07-16

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Yanru Li ,  Michael Hawjing Lo ,  Dexter Tamio Chun

IPC: G11C11/406 ,  G11C7/10 ,  G11C8/12

Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

公开(公告)号：US11126586B2

公开(公告)日：2021-09-21

申请号：US16836982

申请日：2020-04-01

Applicant: QUALCOMM Incorporated

Inventor： Dhamim Packer Ali ,  Sreenivasulu Reddy Chalamcharla ,  Ruchi Parekh ,  Daison Davis Koola ,  Dhaval Patel ,  Eric Taseski ,  Yanru Li ,  Alexander Gantman

IPC: G06F15/177 ,  G06F9/4401 ,  G06F9/445 ,  G05B13/02 ,  G06F1/3293 ,  G06F1/3234 ,  G06F1/324 ,  G06F15/76 ,  G06F21/57 ,  G06F30/30

Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of calibrating a component. The method includes receiving previous calibration parameters for an external component at a secondary SoC from a primary SoC, wherein the secondary SoC is coupled to the external component and configured to calibrate the external component. The method further includes determining validity of the previous calibration parameters by the secondary SoC. The method further includes operating the external component by the secondary SoC based on the determined validity of the previous calibration parameters.

公开(公告)号：US10783252B2

公开(公告)日：2020-09-22

申请号：US16107956

申请日：2018-08-21

Applicant: QUALCOMM Incorporated

Inventor： Yanru Li ,  Azzedine Touzni ,  Dexter Chun

IPC: G06F9/00 ,  G06F15/177 ,  G06F21/57 ,  G06F9/445 ,  G06F9/4401 ,  G06F21/51 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3296 ,  G06F15/78

Abstract: System and methods for booting a system-on-chip (SOC) in an enhanced memory mode are described herein. In one aspect, an enhanced memory mode indicator may be read to create a trusted channel to a non-volatile random-access memory (NVRAM). The NVRAM may be logically connected to the SOC. In an aspect, the NVRAM may be secured prior to the creation of the trusted channel. Once the secure channel to NVRAM has been created, the SOC may operate in an enhanced memory mode. Prior to the SOC powering down, the system may store an indicator operable to enable a subsequent boot of the SOC in the power saving mode. The SOC may be operable to switch between the power saving mode and a normal mode depending on the operational requirements of the portable computing device in which the SOC is implemented.