公开(公告)号：US20210305187A1

公开(公告)日：2021-09-30

申请号：US16836470

申请日：2020-03-31

Applicant: RAYTHEON COMPANY

Inventor： James E. Benedict ,  Paul A. Danello ,  Mikhail Pevzner ,  Thomas V. Sikina ,  Andrew R. Southworth

IPC: H01L23/00

Abstract: A process of fabricating an electromagnetic circuit includes providing a first sheet of dielectric material including a top surface having at least one conductive trace and depositing a solder bump on the at least one conductive trace. The process further includes applying a second sheet of dielectric material to the first sheet of dielectric material with bond film sandwiched in between, the second sheet of dielectric material having a through-hole providing access to the solder bump. The process further includes bonding the first and second dielectric materials to one another and removing bond film resin from the solder bump. The process further includes machining the solder bump by the drilling or milling process to achieve a desired amount of solder in the solder bump.

公开(公告)号：US11089687B2

公开(公告)日：2021-08-10

申请号：US16287260

申请日：2019-02-27

Applicant: RAYTHEON COMPANY

Inventor： Jonathan E. Nufio-Molina ,  Thomas V. Sikina ,  James E. Benedict ,  Andrew R. Southworth ,  Semira M. Azadzoi

IPC: H05K1/02 ,  H05K1/16 ,  H01P5/16 ,  H01C7/00 ,  B33Y80/00

Abstract: A method of manufacturing a power divider circuit includes milling a conductive material disposed upon a first substrate to form a signal trace. The signal trace includes a division from a single trace to two arm traces, with each of the two arm traces having a proximal end electrically connected to the single trace and a distal end electrically connected to each of two secondary traces. The method further includes depositing a resistive ink between the two distal ends to form a resistive electrical connection between the two arm traces, bonding a second substrate to the first substrate to substantially encapsulate the traces between the first substrate and the second substrate, and milling through at least one of the first substrate or the second substrate to provide access to at least one of the traces. A signal divider is further disclosed.

公开(公告)号：US20210144892A1

公开(公告)日：2021-05-13

申请号：US16678211

申请日：2019-11-08

Applicant: RAYTHEON COMPANY

Inventor： Mikhail Pevzner ,  James E. Benedict ,  Andrew R. Southworth ,  Wade A. Schwanda

IPC: H05K13/04 ,  H05K3/38 ,  H05K3/46

Abstract: An apparatus to automatically place layers of a printed circuit board on a fixture includes a robotic device having a base that is secured to a surface, an upright column that extends upwardly from the base, and a movable arm rotatably coupled to the upright column. The movable arm is configured to rotate about a vertical axis defined by the upright column. The movable arm is further configured to rotate from a position in which the movable arm is disposed over a laminate sheet fixture and to pick up a laminate sheet to a position in which the movable arm is disposed over a board layup fixture to deposit the laminate sheet in the board layup fixture, and from a position in which the movable arm is disposed over a bond film fixture and to pick up a bond film to a position in which the movable arm is disposed over the board layup fixture to deposit the bond film in the board layup fixture.

公开(公告)号：US11470725B2

公开(公告)日：2022-10-11

申请号：US17395977

申请日：2021-08-06

Applicant: RAYTHEON COMPANY

Inventor： Mikhail Pevzner ,  James E. Benedict ,  Andrew R. Southworth ,  Thomas V. Sikina ,  Kevin Wilder ,  Matthew Souza ,  Aaron Michael Torberg

IPC: H05K3/10 ,  B21F11/00

Abstract: An apparatus for automating the fabrication of a copper vertical launch (CVL) within a printed circuit board (PCB) includes a feed mechanism to feed and extrude copper wire from a spool of copper wire and a wire cutting and gripping mechanism to receive copper wire from the feed mechanism, cut and secure a segment of copper wire, insert the segment of copper wire into a hole formed within the PCB, solder an end of the segment of copper wire to a signal trace of the PCB, and flush cut an opposite end of the segment of the copper wire to a surface of the PCB. The wire cutting and gripping mechanism includes a wire cutter to flush cut the segment of copper wire and an integrated heated gripper device to receive the copper wire from the spool of copper wire and cut and grab a segment from copper wire.

公开(公告)号：US11444365B2

公开(公告)日：2022-09-13

申请号：US16822399

申请日：2020-03-18

Applicant: RAYTHEON COMPANY

Inventor： James Benedict ,  Erika Klek ,  John P. Haven ,  Michael Souliotis ,  Thomas V. Sikina ,  Andrew R. Southworth ,  Kevin Wilder

IPC: H01P5/08 ,  H01P3/08

Abstract: A RAMP-radio frequency (RAMP-RF) assembly is provided and includes an RF panel including a microstrip interface, a plate including a stripline interface and a microstrip-to-stripline transition element operably connectable to the microstrip interface and to the stripline interface.

公开(公告)号：US20210400820A1

公开(公告)日：2021-12-23

申请号：US17465292

申请日：2021-09-02

Applicant: RAYTHEON COMPANY

Inventor： James E. Benedict ,  Gregory G. Beninati ,  Mikhail Pevzner ,  Thomas V. Sikina ,  Andrew R. Southworth

IPC: H05K3/34 ,  H05K3/00

Abstract: A process of fabricating a circuit includes providing a first sheet of dielectric material including a first top surface having at least one first conductive trace and a second sheet of dielectric material including a second top surface having at least one second conductive trace, depositing a first solder bump on the at least one first conductive trace, applying the second sheet of dielectric material to the first sheet of dielectric material with bonding film sandwiched in between, bonding the first and second sheets of dielectric material to one another, and providing a conductive material to connect the first solder bump on the at least one first conductive trace to the at least one second conductive trace.

公开(公告)号：US11171101B2

公开(公告)日：2021-11-09

申请号：US16836470

申请日：2020-03-31

Applicant: RAYTHEON COMPANY

Inventor： James E. Benedict ,  Paul A. Danello ,  Mikhail Pevzner ,  Thomas V. Sikina ,  Andrew R. Southworth

IPC: H01L23/00

Abstract: A process of fabricating an electromagnetic circuit includes providing a first sheet of dielectric material including a top surface having at least one conductive trace and depositing a solder bump on the at least one conductive trace. The process further includes applying a second sheet of dielectric material to the first sheet of dielectric material with bond film sandwiched in between, the second sheet of dielectric material having a through-hole providing access to the solder bump. The process further includes bonding the first and second dielectric materials to one another and removing bond film resin from the solder bump. The process further includes machining the solder bump by the drilling or milling process to achieve a desired amount of solder in the solder bump.

公开(公告)号：US11158955B2

公开(公告)日：2021-10-26

申请号：US16183116

申请日：2018-11-07

Applicant: RAYTHEON COMPANY

Inventor： Thomas V. Sikina ,  John P. Haven ,  James E. Benedict ,  Jonathan E. Nufio-Molina ,  Andrew R. Southworth

IPC: H01Q1/52 ,  H01Q21/00 ,  H01P1/04 ,  H01Q13/10 ,  H01Q13/18 ,  H05K1/02 ,  H05K3/40 ,  H01P5/02 ,  H01Q17/00 ,  H01Q1/42 ,  H01Q1/44 ,  B33Y10/00 ,  B33Y70/00 ,  B33Y80/00

Abstract: A low profile array (LPA) includes an antenna element array layer having at least one Faraday wall, and a beamformer circuit layer coupled to the antenna element array layer. The beamformer circuit layer has at least one Faraday wall. The Faraday walls extends between ground planes associated with at least one of the antenna element array layer and the beamformer circuit layer.

公开(公告)号：US20210151855A1

公开(公告)日：2021-05-20

申请号：US16683593

申请日：2019-11-14

Applicant: RAYTHEON COMPANY

Inventor： Thomas V. Sikina ,  John P. Haven ,  Kevin Wilder ,  James E. Benedict ,  Andrew R. Southworth ,  Mary K. Herndon

IPC: H01Q1/24 ,  H01Q21/00 ,  H01Q21/06 ,  H01Q1/52

Abstract: A communications array includes a support structure configured to array elements, and a plurality of array elements supported by the support structure. Each array element is fabricated from an advanced manufacturing techniques (AMT) process. The support structure may be fabricated from a printed circuit board (PCB) or similar dielectric material. Each array element may include a radiator and/or a beamformer manufactured using the AMT process. The communications array further may include a copper vertical launch (CVL) and/or an electromagnetic boundary.

公开(公告)号：US20210144864A1

公开(公告)日：2021-05-13

申请号：US16678188

申请日：2019-11-08

Applicant: RAYTHEON COMPANY

Inventor： Mikhail Pevzner ,  Gregory G. Beninati ,  James E. Benedict ,  Andrew R. Southworth

IPC: H05K3/46

Abstract: A process of fabricating an electromagnetic circuit includes providing three laminate sheets, forming a first feature in a first laminate sheet of the three laminate sheets, and forming a second feature in a second laminate sheet of the three laminate sheets. The second feature is aligned with the first feature when aligning the second laminate sheet with the first laminate sheet. The process further includes stacking the three laminate sheets so that the first laminate sheet is positioned above and aligned with the second laminate sheet and the second laminate sheet is positioned above and aligned with the third laminate sheet. The first feature and the second feature define a contiguous element. The process further includes filling the contiguous element with an electrically conductive material to form an electrically continuous conductor.