公开(公告)号：US20190123233A1

公开(公告)日：2019-04-25

申请号：US16057858

申请日：2018-08-08

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya USAMI

IPC: H01L31/18 ,  H01L31/0216 ,  H01L31/0352 ,  H01L31/109 ,  H01L31/02 ,  H01L31/028

CPC classification number: H01L31/1804 ,  H01L31/02005 ,  H01L31/02161 ,  H01L31/028 ,  H01L31/035281 ,  H01L31/109

Abstract: A method of manufacturing the semiconductor device includes: (a) providing a substrate having a semiconductor layer; (b) forming a first insulating film over an insulating layer so as to cover the semiconductor layer; (c) forming an opening extending through the first insulating film and reaching the semiconductor layer; (d) forming, over the semiconductor layer exposed at a bottom surface of the opening, a semiconductor portion having a thickness smaller than that of the first insulating film over the semiconductor layer by a selective epitaxial growth method; (e) forming a second insulating film over the first insulating film and the semiconductor portion; (f) removing the second insulating film from over the first insulating film, while leaving the second insulating film in the opening; (g) removing a semiconductor particle formed over the first insulating film in the (d); and (h) forming a third insulating film over the first insulating film.

公开(公告)号：US20180151410A1

公开(公告)日：2018-05-31

申请号：US15795051

申请日：2017-10-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya USAMI

IPC: H01L21/74 ,  H01L21/308 ,  H01L21/285 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L21/743 ,  H01L21/28518 ,  H01L21/308 ,  H01L21/76879 ,  H01L29/7816

Abstract: To improve the characteristics of a semiconductor device having a substrate contact formed in a deep trench. In a method of forming a plug PSUB in a deep trench DT2 that penetrates an n-type buried layer NBL and reaches a p-type epitaxial layer PEP1, the plug PSUB is formed in the deep trench DT2 after a metal silicide layer SIL1 is formed in the p-type epitaxial layer PEP1. The metal silicide layer SIL1 is formed using a PVD-first metal film (a first metal film formed by PVD). A first barrier metal film BM1 at the bottom of the plug PSUB is a CVD-second metal film (a second metal film formed by CVD). The first metal film is a metal film different from the second metal film.

公开(公告)号：US20180130900A1

公开(公告)日：2018-05-10

申请号：US15786366

申请日：2017-10-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya USAMI

IPC: H01L29/786 ,  H01L21/764 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/12

CPC classification number: H01L21/762 ,  H01L21/28518 ,  H01L21/743 ,  H01L21/764 ,  H01L21/8234 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/0649

Abstract: To provide a semiconductor device having a substrate contact in a deep trench thereof and having an improved characteristic. A PVD-metal film (metal film formed by PVD) is used as a first barrier metal film which is a lowermost layer barrier metal film formed in a deep trench penetrating an n type epitaxial layer and a reaching a layer therebelow. Such a configuration makes it possible to stably form a metal silicide layer at a boundary between the PVD-metal film and a silicon layer therebelow (or silicon substrate) and thereby stabilize the contact resistance.

公开(公告)号：US20170287934A1

公开(公告)日：2017-10-05

申请号：US15462814

申请日：2017-03-18

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya USAMI

IPC: H01L27/12 ,  H01L21/84 ,  G02B6/132 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/48 ,  H01L23/34 ,  H01L23/538

CPC classification number: H01L27/1203 ,  G02B6/132 ,  G02B2006/12061 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/4853 ,  H01L21/84 ,  H01L23/345 ,  H01L23/5386

Abstract: An optical waveguide for optical signals is formed in a semiconductor layer of an SOI substrate, a heater for heating the optical waveguide is formed on a silicon oxide film which covers the optical waveguide, and wirings for supplying power to the heater are connected to both ends of the heater. Each of the wirings is constituted of a laminated film of a bottom barrier metal film, an aluminum-copper alloy film serving as a main conductive film and a top barrier metal film, and the heater is constituted integrally with the bottom barrier metal film constituting a part of each of the wirings.

公开(公告)号：US20160370542A1

公开(公告)日：2016-12-22

申请号：US15174981

申请日：2016-06-06

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya USAMI

IPC: G02B6/13 ,  G02B6/122

CPC classification number: G02B6/13 ,  G02B6/12004 ,  G02B6/122 ,  G02B6/1223 ,  G02B6/132 ,  G02B6/43 ,  G02B2006/12038 ,  G02B2006/12061 ,  G02F1/0121 ,  G02F1/025 ,  G02F2202/104 ,  H01L31/02325 ,  H01L31/02327 ,  H01L31/18

Abstract: An SOI substrate is attracted to and detached from an electrostatic chuck included in a semiconductor manufacturing device without failures. A semiconductor device includes a semiconductor substrate made of silicon, a first insulating film formed on a main surface of the semiconductor substrate and configured to generate compression stress to silicon, a waveguide, made of silicon, formed on the first insulating film, and a first interlayer insulating film formed on the first insulating film so as to cover the waveguide. Further, a second insulating film configured to generate tensile stress to silicon is formed on the first interlayer insulating film and in a region distant from the optical waveguide by a thickness of the first insulating film or larger. The second insulating film offsets the compression of the first insulating film.

Abstract translation: SOI衬底被吸引到包括在半导体制造装置中的静电吸盘并从其分离，而不会发生故障。 半导体器件包括由硅制成的半导体衬底，形成在半导体衬底的主表面上并被配置为对硅产生压缩应力的第一绝缘膜，形成在第一绝缘膜上的由硅制成的波导，以及第一绝缘膜 形成在第一绝缘膜上以覆盖波导的层间绝缘膜。 此外，在第一层间绝缘膜上和远离光波导的区域中形成厚度为第一绝缘膜的较大的第二绝缘膜。 第二绝缘膜抵消第一绝缘膜的压缩。

公开(公告)号：US20160293481A1

公开(公告)日：2016-10-06

申请号：US15068547

申请日：2016-03-12

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya USAMI ,  Keiji SAKAMOTO ,  Hiroyuki KUNISHIMA

IPC: H01L21/768 ,  G02B6/134 ,  G02B6/136 ,  G02F1/025 ,  H01L23/544 ,  G02B6/122

CPC classification number: G02B6/1347 ,  G02B6/12004 ,  G02B6/122 ,  G02B6/136 ,  G02B2006/12061 ,  G02B2006/121 ,  G02F1/025 ,  H01L23/562

Abstract: A rectangular optical waveguide, an optical phase shifter and an optical modulator each formed of a semiconductor layer are formed on an insulating film constituting an SOI wafer, and then a rear insulating film formed on a rear surface of the SOI wafer is removed. Moreover, a plurality of trenches each having a first depth from an upper surface of the insulating film are formed at a position not overlapping with the rectangular optical waveguide, the optical phase shifter and the optical modulator when seen in a plan view in the insulating film. As a result, since an electric charge can be easily released from the SOI wafer even when the SOI wafer is later mounted on the electrostatic chuck included in the semiconductor manufacturing apparatus, the electric charge is less likely to be accumulated on the rear surface of the SOI wafer.

Abstract translation: 在构成SOI晶片的绝缘膜上形成由半导体层形成的矩形光波导，光学移相器和光调制器，然后去除形成在SOI晶片的后表面上的后绝缘膜。 此外，在绝缘膜的平面图中看到，在与矩形光波导，光移相器和光调制器不重叠的位置处形成有从绝缘膜的上表面开始的第一深度的多个沟槽 。 结果，即使当SOI晶片后来安装在包括在半导体制造装置中的静电卡盘上时，也可以容易地从SOI晶片释放电荷，所以电荷不太可能积聚在半导体制造装置的背面 SOI晶圆。

公开(公告)号：US20150372102A1

公开(公告)日：2015-12-24

申请号：US14714958

申请日：2015-05-18

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya USAMI

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/41775 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/53295 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

Abstract: The parasitic capacitance formed by a gate electrode, a contact, and a side wall is reduced.The gate electrode and the side wall are covered by an insulating layer. The contact passes through the insulating layer and is connected to a diffusion layer. Then, an air gap is located between the side wall and the contact. The air gap faces the contact at the side face on the contact side via the insulating layer.

Abstract translation: 由栅电极，触点和侧壁形成的寄生电容减小。 栅电极和侧壁被绝缘层覆盖。 接触通过绝缘层并连接到扩散层。 然后，气隙位于侧壁和接触件之间。 气隙经由绝缘层与接触侧的侧面接触。