公开(公告)号：US20170186763A1

公开(公告)日：2017-06-29

申请号：US15384602

申请日：2016-12-20

Applicant: Renesas Electronics Corporation

Inventor： Tatsuyoshi MIHARA

IPC: H01L27/11568 ,  H01L29/792 ,  H01L29/423

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/42376 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7853 ,  H01L29/7855 ,  H01L29/792 ,  H01L29/7923

Abstract: A fin includes a first region and a second region arranged on a positive side in an X-axis direction with respect to the first region. A control gate electrode covers an upper surface of the first region, and a side surface of the first region on the positive side in a Y-axis direction. A memory gate electrode covers an upper surface of the second region, and a side surface of the second region on the positive side in the Y-axis direction. The upper surface of the second region is lower than the upper surface of the first region. The side surface of the second region is arranged on the negative side in the Y-axis direction with respect to the side surface of the first region in the Y-axis direction.

公开(公告)号：US20170154884A1

公开(公告)日：2017-06-01

申请号：US15429512

申请日：2017-02-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuyoshi MIHARA

IPC: H01L27/06 ,  G11C16/04 ,  H01L29/792 ,  H01L27/11565 ,  H01L29/66 ,  H01L27/11568

CPC classification number: H01L27/0629 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  H01L21/823468 ,  H01L27/1104 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

Abstract: The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed.

公开(公告)号：US20160043200A1

公开(公告)日：2016-02-11

申请号：US14921445

申请日：2015-10-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuyoshi MIHARA

IPC: H01L29/66

CPC classification number: H01L27/0629 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  H01L21/823468 ,  H01L27/1104 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

Abstract: The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed.

Abstract translation: 实现具有分割门型MONOS存储器的半导体器件的可靠性的提高。 依次形成ONO膜和第二多晶硅膜，以填充第一多晶硅膜和虚拟栅电极。 然后，去除虚拟栅电极。 然后，对第一多晶硅膜和第二多晶硅膜的顶表面进行抛光，从而在由第一多晶硅膜经由ONO膜形成的控制栅电极的侧壁处形成由第二多晶硅膜形成的存储栅电极。 结果，形成了侧壁高度垂直的存储栅电极，膜厚度均匀。

公开(公告)号：US20140065776A1

公开(公告)日：2014-03-06

申请号：US13964576

申请日：2013-08-12

Applicant: Renesas Electronics Corporation

Inventor： Tatsuyoshi MIHARA

IPC: H01L29/66

CPC classification number: H01L27/0629 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  H01L21/823468 ,  H01L27/1104 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

Abstract: The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed.

Abstract translation: 实现具有分割门型MONOS存储器的半导体器件的可靠性的提高。 依次形成ONO膜和第二多晶硅膜，以填充第一多晶硅膜和虚拟栅电极。 然后，去除虚拟栅电极。 然后，对第一多晶硅膜和第二多晶硅膜的顶表面进行抛光，从而在由第一多晶硅膜经由ONO膜形成的控制栅电极的侧壁处形成由第二多晶硅膜形成的存储栅电极。 结果，形成了侧壁高度垂直的存储栅电极，膜厚度均匀。

公开(公告)号：US20220068706A1

公开(公告)日：2022-03-03

申请号：US17369714

申请日：2021-07-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MAEDA ,  Tatsuyoshi MIHARA ,  Hiroki SHINKAWATA

IPC: H01L21/762 ,  H01L27/11 ,  H01L27/12 ,  H01L21/304

Abstract: Gate patterns are formed on a semiconductor layer and a conductive film is formed on the semiconductor layer so as to cover the gate patterns. By performing a polishing process to the conductive film and patterning the polished conductive film, pad layers are formed between the gate patterns via sidewall spacers.

公开(公告)号：US20210257217A1

公开(公告)日：2021-08-19

申请号：US16793573

申请日：2020-02-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuyoshi MIHARA

IPC: H01L21/285 ,  H01L27/12 ,  H01L29/45 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84

Abstract: After a MISFET is formed on a substrate including a semiconductor substrate, an insulating layer and a semiconductor layer, an interlayer insulating film and a first insulating film are formed on the substrate. Also, after an opening is formed in each of the first insulating film and the interlayer insulating film, a second insulating film is formed at each of a bottom portion of the opening and a side surface of the opening and also formed on an upper surface of the first insulating film. Further, each of the second insulating film formed at the bottom portion of the opening and the second insulating film formed on the upper surface of the first insulating film is removed by etching. After that, an inside of the opening is etched under a condition that each of the first insulating film and the second insulating film is less etched than the insulating layer.

公开(公告)号：US20190103413A1

公开(公告)日：2019-04-04

申请号：US16189373

申请日：2018-11-13

Applicant: Renesas Electronics Corporation

Inventor： Tatsuyoshi MIHARA

IPC: H01L27/11568 ,  H01L27/11573 ,  H01L29/78 ,  H01L29/792 ,  H01L29/423 ,  H01L27/11575 ,  H01L21/28

Abstract: To improve reliability of a semiconductor device, a control transistor and a memory transistor formed in a memory cell region are configured to have a double-gate structure, and a transistor formed in a peripheral circuit region is configured to have a triple-gate structure. For example, in the memory transistor, a gate insulating film formed by an ONO film is provided between a memory gate electrode and sidewalls of a fin, and an insulating film (a stacked film of a multilayer film of an insulating film/an oxide film and the ONO film) thicker than the ONO film is provided between the memory gate electrode and a top surface of the fin. This configuration can reduce concentration of an electric field onto a tip of the fin, so that deterioration of reliability of the ONO film can be prevented.

公开(公告)号：US20180182768A1

公开(公告)日：2018-06-28

申请号：US15831123

申请日：2017-12-04

Applicant: Renesas Electronics Corporation

Inventor： Tatsuyoshi MIHARA

IPC: H01L27/1157 ,  H01L29/792 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L21/3213

CPC classification number: H01L27/1157 ,  H01L21/3086 ,  H01L21/32134 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/4933 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/7855 ,  H01L29/792

Abstract: After a dummy control gate electrode and a memory gate electrode are formed and an interlayer insulating film is formed so as to cover the gate electrodes, the interlayer insulating film is polished to expose the dummy control gate electrode and the memory gate electrode. Thereafter, the dummy control gate electrode is removed by etching, and then a control gate electrode is formed in a trench which is a region from which the dummy control gate electrode has been removed. The dummy control gate electrode is made of a non-doped or n type silicon film, and the memory gate electrode is made of a p type silicon film. In the process of removing the dummy control gate electrode, the dummy control gate electrode is removed by performing etching under the condition that the memory gate electrode is less likely to be etched compared with the dummy control gate electrode, in the state where the dummy control gate electrode and the memory gate electrode are exposed.

公开(公告)号：US20170309755A1

公开(公告)日：2017-10-26

申请号：US15648431

申请日：2017-07-12

Applicant: Renesas Electronics Corporation

Inventor： Tatsuyoshi MIHARA

IPC: H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor substrate including a main surface, an element separation film formed over the main surface, and a fin protruding from the element separation film and extending in the first direction in plan view. The semiconductor device further includes a control gate electrode extending in the second direction that is orthogonal to the first direction along the surface of the fin through a gate insulating film and overlaps with a first main surface of the element separation film, and a memory gate electrode extending in the second direction along the surface of the fin through an insulating film and overlaps with a second main surface of the element separation film, in which the second main surface is lower than the first main surface relative to the main surface.

公开(公告)号：US20170243982A1

公开(公告)日：2017-08-24

申请号：US15378352

申请日：2016-12-14

Applicant: Renesas Electronics Corporation

Inventor： Tatsuyoshi MIHARA

IPC: H01L29/792 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor substrate including a main surface, an element separation film formed over the main surface, and a fin protruding from the element separation film and extending in the first direction in plan view. The semiconductor device further includes a control gate electrode extending in the second direction that is orthogonal to the first direction along the surface of the fin through a gate insulating film and overlaps with a first main surface of the element separation film, and a memory gate electrode extending in the second direction along the surface of the fin through an insulating film and overlaps with a second main surface of the element separation film, in which the second main surface is lower than the first main surface relative to the main surface.