公开(公告)号：US20220269436A1

公开(公告)日：2022-08-25

申请号：US17627478

申请日：2020-07-06

Applicant: Rambus Inc.

Inventor： Mark D. KELLAM ,  Steven C. WOO ,  Thomas VOGELSANG ,  John Eric LINSTADT

IPC: G06F3/06

Abstract: An integrated circuit that includes a set of one or more logic layers that are, when the integrated circuit is stacked in an assembly with the set of stacked memory devices, electrically coupled to a set of stacked memory devices. The set of one or more logic layers include a coupled chain of processing elements. The processing elements in the coupled chain may independently compute partial results as functions of data received, store partial results, and pass partial results directly to a next processing element in the coupled chain of processing elements. The processing elements in the chains may include interfaces that allow direct access to memory banks on one or more DRAMs in the stack. These interfaces may access DRAM memory banks via TSVs that are not used for global I/O. These interfaces allow the processing elements to have more direct access to the data in the DRAM.

公开(公告)号：US20220013161A1

公开(公告)日：2022-01-13

申请号：US17390370

申请日：2021-07-30

Applicant: Rambus Inc.

Inventor： Thomas VOGELSANG ,  John Eric LINSTADT ,  Liji GOPALAKRISHNAN

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4091 ,  G06F13/42

Abstract: A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.

公开(公告)号：US20240320080A1

公开(公告)日：2024-09-26

申请号：US18586907

申请日：2024-02-26

Applicant: Rambus Inc.

Inventor： Thomas J. GIOVANNINI ,  Catherine CHEN ,  Scott C. BEST ,  John Eric LINSTADT ,  Frederick A. WARE

IPC: G06F11/07 ,  G06F13/00 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26 ,  G11C29/44

CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/0772 ,  G06F13/00 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26 ,  G11C29/44

Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

公开(公告)号：US20240241791A1

公开(公告)日：2024-07-18

申请号：US18497161

申请日：2023-10-30

Applicant: Rambus Inc.

Inventor： John Eric LINSTADT

IPC: G06F11/10

CPC classification number: G06F11/1076

Abstract: A programmable crossbar matrix or an array of steering multiplexors (MUXs) coalesces (i.e., routes) the data values from multiple known “bad” bit positions within multiple symbols of a codeword, to bit positions within a single codeword symbol. The single codeword symbol receiving the known “bad” bit positions may correspond to a check symbol (vs. a data symbol). Configuration of the routing logic may occur at boot or initialization time. The configuration of the routing logic may be based upon error mapping information retrieved from system non-volatile memory (e.g., memory module serial presence detect information), or from memory tests performed during initialization. The configuration of the routing logic may be changed on a per-rank basis.

公开(公告)号：US20240036754A1

公开(公告)日：2024-02-01

申请号：US18230413

申请日：2023-08-04

Applicant: Rambus Inc.

Inventor： Frederick A. WARE ,  John Eric LINSTADT

IPC: G06F3/06 ,  G11C11/4091 ,  G11C11/4076 ,  G11C7/06 ,  G11C7/22 ,  G11C7/18 ,  G11C11/4097

CPC classification number: G06F3/064 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/0655 ,  G06F3/0673 ,  G11C11/4091 ,  G11C11/4076 ,  G11C7/06 ,  G11C7/22 ,  G11C7/18 ,  G11C11/4097

Abstract: Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than a second format. In this manner, the data blocks stored in the first format can be accessed with lower latency than the blocks stored in the second format because more data can be read from the array simultaneously. In addition, since the data stored in the second format is stored in fewer subarrays, it takes less energy to read a block stored in the second format. Thus, a system may elect, on a data block by data block basis, whether to conserve power or improve speed.

公开(公告)号：US20240012709A1

公开(公告)日：2024-01-11

申请号：US18036246

申请日：2021-11-16

Applicant: Rambus Inc.

Inventor： Craig E. HAMPEL ,  John Eric LINSTADT

IPC: G06F11/10

CPC classification number: G06F11/10

Abstract: A multi-host processing system may access memory devices (e.g., memory modules, memory integrated circuits, etc.) via memory nodes having memory controllers. The memory controllers may be configured to use more than one error control scheme when accessing the same memory devices. The selection of the error control scheme may be made based on the interface receiving the memory transaction request. The selection of the error control scheme may be made based on information in the memory transaction request. The selection of the error control scheme may be made based on the fabric physical address and a lookup table or address range registers. The selection of the error control scheme may be made based on the memory device physical address and a lookup table or address range registers.

公开(公告)号：US20230161668A1

公开(公告)日：2023-05-25

申请号：US18070732

申请日：2022-11-29

Applicant: Rambus Inc.

Inventor： John Eric LINSTADT

IPC: G06F11/10

CPC classification number: G06F11/1076

Abstract: A programmable crossbar matrix or an array of steering multiplexors (MUXs) coalesces (i.e., routes) the data values from multiple known “bad” bit positions within multiple symbols of a codeword, to bit positions within a single codeword symbol. The single codeword symbol receiving the known “bad” bit positions may correspond to a check symbol (vs. a data symbol). Configuration of the routing logic may occur at boot or initialization time. The configuration of the routing logic may be based upon error mapping information retrieved from system non-volatile memory (e.g., memory module serial presence detect information), or from memory tests performed during initialization. The configuration of the routing logic may be changed on a per-rank basis.

公开(公告)号：US20220357846A1

公开(公告)日：2022-11-10

申请号：US17831576

申请日：2022-06-03

Applicant: Rambus Inc.

Inventor： Frederick A. WARE ,  John Eric LINSTADT

IPC: G06F3/06 ,  G11C11/4091 ,  G11C11/4076 ,  G11C7/06 ,  G11C7/22 ,  G11C7/18 ,  G11C11/4097

Abstract: Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than a second format. In this manner, the data blocks stored in the first format can be accessed with lower latency than the blocks stored in the second format because more data can be read from the array simultaneously. In addition, since the data stored in the second format is stored in fewer subarrays, it takes less energy to read a block stored in the second format. Thus, a system may elect, on a data block by data block basis, whether to conserve power or improve speed.

公开(公告)号：US20220328078A1

公开(公告)日：2022-10-13

申请号：US17634370

申请日：2020-08-13

Applicant: Rambus Inc.

Inventor： John Eric LINSTADT ,  Liji GOPALAKRISHNAN ,  Thomas VOGELSANG

IPC: G11C7/10 ,  G11C7/22

Abstract: The memory banks of a memory device are arranged and operated in groups and the groups are further arranged and operated as clusters of these groups. Successive accesses to banks that are within different bank group clusters may be issued at a first time interval. Successive accesses to banks that are within different bank groups within the same cluster can be issued no faster than a second time interval. And, successive accesses to banks that are within the same bank group may be issued no faster than a third time interval. The memory banks of a memory device may have multiple rows open at the same time. The rows that can be open at the same time is determined by the rows that are already open. These memory banks are also arranged and operated in groups that have three different minimum time intervals.

公开(公告)号：US20210375354A1

公开(公告)日：2021-12-02

申请号：US17325977

申请日：2021-05-20

Applicant: Rambus Inc.

Inventor： Torsten PARTSCH ,  John Eric LINSTADT ,  Helena HANDSCHUH

IPC: G11C11/406 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4076

Abstract: A block of dynamic memory in a DRAM device is organized to share a common set of bitlines may be erased/destroyed/randomized by concurrently activating multiple (or all) of the wordlines of the block. The data held in the sense amplifiers and cells of an active wordline may be erased by precharging the sense amplifiers and then writing precharge voltages into the cells of the open row. Rows are selectively configured to either be refreshed or not refreshed. The rows that are not refreshed will, after a time, lose their contents thereby reducing the time interval for attack. An external signal can cause the isolation of a memory device or module and initiation of automatic erasure of the memory contents of the device or module using one of the methods disclosed herein. The trigger for the external signal may be one or more of temperature changes/conditions, loss of power, and/or external commands from a controller.