公开(公告)号：US20190180805A1

公开(公告)日：2019-06-13

申请号：US16215573

申请日：2018-12-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Brian S. Leibowitz ,  Wayne Frederick Ellis ,  Akash Bansal ,  John Welsford Brooks ,  Kishore Ven Kasamsetty

IPC: G11C8/18 ,  G06F13/16 ,  G11C7/10 ,  G11C29/02 ,  G06F13/42 ,  G11C5/02

Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

公开(公告)号：US10170170B2

公开(公告)日：2019-01-01

申请号：US15798136

申请日：2017-10-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Brian S. Leibowitz ,  Wayne Frederick Ellis ,  Akash Bansal ,  John Welsford Brooks ,  Kishore Ven Kasamsetty

IPC: G11C8/18 ,  G11C7/10 ,  G11C5/02 ,  G11C29/02 ,  G06F13/16 ,  G06F13/42 ,  G11C5/04

Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

公开(公告)号：US20180137914A1

公开(公告)日：2018-05-17

申请号：US15817887

申请日：2017-11-20

Applicant: Rambus Inc.

Inventor： Deepak Chandra Sekar ,  Wayne Frederick Ellis

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C5/02 ,  G11C5/06 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2013/0088 ,  G11C2213/79 ,  G11C2213/82

Abstract: A memory device includes an array of resistive memory cells wherein each pair of resistive memory cells includes a first switching element electrically coupled in series to a first resistive memory element and a second switching element electrically coupled in series to a second resistive memory element. A source of the first switching element and a source of the second switching element receive a common source line signal.

公开(公告)号：US09965012B2

公开(公告)日：2018-05-08

申请号：US15017395

申请日：2016-02-05

Applicant: Rambus Inc.

Inventor： Deborah Lindsey Dressler ,  Julia Kelly Cline ,  Wayne Frederick Ellis

IPC: G06F1/32 ,  G11C5/14 ,  G06F1/28 ,  G11C5/06 ,  G06F13/42

CPC classification number: G06F1/28 ,  G06F1/3275 ,  G06F1/3287 ,  G06F13/4273 ,  G11C5/063

Abstract: A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes sideband circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.

公开(公告)号：US20170133070A1

公开(公告)日：2017-05-11

申请号：US15390681

申请日：2016-12-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Brian S. Leibowitz ,  Wayne Frederick Ellis ,  Akash Bansal ,  John Welsford Brooks ,  Kishore Ven Kasamsetty

IPC: G11C8/18 ,  G06F13/16 ,  G06F13/42 ,  G11C7/10

CPC classification number: G11C8/18 ,  G06F13/161 ,  G06F13/1647 ,  G06F13/1657 ,  G06F13/4234 ,  G11C5/02 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1072 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

公开(公告)号：US20160078934A1

公开(公告)日：2016-03-17

申请号：US14567988

申请日：2014-12-11

Applicant: Rambus Inc.

Inventor： Deepak Chandra Sekar ,  Wayne Frederick Ellis

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C5/02 ,  G11C5/06 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2013/0088 ,  G11C2213/79 ,  G11C2213/82

Abstract: A memory device includes an array of resistive memory cells wherein each pair of resistive memory cells includes a first switching element electrically coupled in series to a first resistive memory element and a second switching element electrically coupled in series to a second resistive memory element. A source of the first switching element and a source of the second switching element receive a common source line signal.

Abstract translation: 存储器件包括电阻存储器单元阵列，其中每对电阻存储器单元包括与第一电阻存储器元件串联电耦合的第一开关元件和与第二电阻存储元件串联电耦合的第二开关元件。 第一开关元件的源极和第二开关元件的源接收公共源极线信号。