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公开(公告)号：US20050105335A1
公开(公告)日：2005-05-19
申请号：US10944910
申请日：2004-09-21
IPC分类号： G11C16/06 , G11C5/02 , G11C5/06 , G11C8/10 , G11C8/12 , G11C16/00 , G11C16/04 , G11C16/08 , H01L21/8247 , H01L27/00 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
摘要： A semiconductor memory device having: a cell array including bit lines, word lines and memory cells disposed at crossings thereof, plural memory cells being connected in series to constitute a NAND cell unit, plural blocks being arranged, each being constituted by plural NAND cell units arranged in the word line direction; and a row decoder configured to select a block, wherein the row decoder includes: transferring transistor arrays disposed in association with the blocks, in each of which transistors are arranged for transferring word line drive voltages; first decode portions disposed in association with the transferring transistor arrays, which are applied with boosted voltages to selectively drive the transferring transistor arrays; and second decode portions configured to select one of the blocks, each of which is disposed to be shared by adjacent two first decode portions.
摘要翻译： 一种半导体存储器件，具有：包括位线，字线和位于其交叉处的存储单元的单元阵列，多个存储单元串联连接以构成NAND单元单元，多个块被布置，每个由多个NAND单元单元 排列在字线方向; 以及配置为选择块的行解码器，其中所述行解码器包括：传送与所述块相关联地布置的晶体管阵列，其中每个晶体管布置用于传送字线驱动电压; 与传输晶体管阵列相关联地设置的第一解码部分，其被施加升压电压以选择性地驱动传输晶体管阵列; 以及第二解码部分，被配置为选择所述块之一，每个块被布置为由相邻的两个第一解码部分共享。
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公开(公告)号：US06590255B2
公开(公告)日：2003-07-08
申请号：US09916595
申请日：2001-07-30
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/11 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11529 , H01L27/11531 , H01L27/11541 , H01L27/11543
摘要： An element isolating region for separating an element region of a semiconductor layer is formed in a peripheral circuit section of a semiconductor memory device, and a first conductive layer is formed with the element region with a first insulating film interposed therebetween. A second conductive layer is formed on the first conductive layer to extend into the element isolating region. A surface of that section of the second conductive layer which is positioned within the element isolating region is exposed, and a third conductive layer is formed on the second conductive layer with a second insulating film interposed therebetween. Further, a contact is electrically connected to an exposed surface of the second conductive layer.
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23.发明授权Semiconductor memory device equipped with memory transistor and peripheral transistor and method of manufacturing the same 失效配有存储晶体管和外围晶体管的半导体存储器件及其制造方法公开(公告)号：US07563664B2
公开(公告)日：2009-07-21
申请号：US11434059
申请日：2006-05-16
IPC分类号： H01L21/8329
CPC分类号： H01L27/11526 , H01L21/823842 , H01L21/82385 , H01L27/105 , H01L27/11529 , H01L27/11546
摘要： A semiconductor memory device provided with a memory cell region having first gate electrodes and a peripheral circuit region having second gate electrodes includes first gate electrodes arranged a first distance apart from each other on a semiconductor substrate, second gate electrodes arranged a second distance, which is larger than the first distance, apart from each other on the semiconductor substrate, first diffusion layers formed in the semiconductor substrate, the first diffusion layers sandwiching the first gate electrodes, second diffusion layers formed in the semiconductor substrate, the second diffusion layers sandwiching the second gate electrodes, a first insulating film formed on the first diffusion layer, second insulating films formed on the side surfaces of the second gate electrodes, first silicide films formed on the first gate electrodes, second silicide films formed on the second gate electrodes, and third silicide films formed on the second diffusion layers.
摘要翻译： 具有具有第一栅电极的存储单元区域和具有第二栅电极的外围电路区域的半导体存储器件包括在半导体衬底上彼此间隔开第一距离布置的第一栅电极，第二栅电极布置成第二距离， 大于第一距离，在半导体衬底上彼此分开，形成在半导体衬底中的第一扩散层，夹着第一栅极的第一扩散层，形成在半导体衬底中的第二扩散层，夹在第二扩散层中的第二扩散层 栅电极，形成在第一扩散层上的第一绝缘膜，形成在第二栅电极的侧表面上的第二绝缘膜，形成在第一栅电极上的第一硅化物膜，形成在第二栅极上的第二硅化物膜，以及第三绝缘膜， 形成在第二扩散层上的硅化物膜。
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公开(公告)号：US20060250849A1
公开(公告)日：2006-11-09
申请号：US11480460
申请日：2006-07-05
IPC分类号： G11C16/04
CPC分类号： H01L27/11521 , G11C16/04 , G11C16/0433 , G11C16/0483 , H01L27/115 , H01L27/11524
摘要： A semiconductor integrated circuit device includes a semiconductor substrate, an element isolation region, a first interconnection, a second interconnection, and a memory cell unit connected between a corresponding one of the first interconnection and a second interconnection. The memory cell unit includes two selection transistors and memory cell transistors of not larger than two. The memory cell transistors are connected between the two selection transistors. The memory cell transistor has a charge storage layer whose side surface lies in the same plane or in substantially the same plane as the side surface of the element isolation regions.
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公开(公告)号：US06995425B2
公开(公告)日：2006-02-07
申请号：US10455427
申请日：2003-06-06
IPC分类号： H01L29/792 , H01L29/788 , H01L29/00 , H01L23/48
CPC分类号： H01L27/11526 , H01L27/11 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11529 , H01L27/11531 , H01L27/11541 , H01L27/11543
摘要： An element isolating region for separating an element region of a semiconductor layer is formed in a peripheral circuit section of a semiconductor memory device, and a first conductive layer is formed with the element region with a first insulating film interposed therebetween. A second conductive layer is formed on the first conductive layer to extend into the element isolating region. A surface of that section of the second conductive layer which is positioned within the element isolating region is exposed, and a third conductive layer is formed on the second conductive layer with a second insulating film interposed therebetween. Further, a contact is electrically connected to an exposed surface of the second conductive layer.
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公开(公告)号：US06894341B2
公开(公告)日：2005-05-17
申请号：US10326179
申请日：2002-12-23
申请人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
发明人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L31/0328
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.
摘要翻译： 半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫 在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能 仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。
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公开(公告)号：US08541829B2
公开(公告)日：2013-09-24
申请号：US13235948
申请日：2011-09-19
IPC分类号： H01L29/76 , H01L29/792
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/0433 , G11C16/0483 , G11C16/30 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on a high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on source and drain regions of each of the memory cell transistor, the low voltage transistor, and the high voltage transistor.
摘要翻译： 非易失性半导体存储器包括：存储单元晶体管，包括形成在第一隧穿绝缘膜上的第一浮栅电极层，第一栅间绝缘膜，第一和第二控制栅极电极层以及第一金属硅化物膜; 包括形成在高压栅极绝缘膜上的高电压栅极电极层，具有孔径的第二栅极间绝缘膜，第三和第四控制栅极电极层以及第二金属硅化物膜的高压晶体管; 包括形成在第二隧道绝缘膜上的第二浮栅电极层，具有孔的第三栅间绝缘膜，第五和第六控制栅电极层和第三金属硅化物膜的低压晶体管; 以及直接设置在每个存储单元晶体管，低压晶体管和高压晶体管的源极和漏极区域上的衬垫绝缘膜。
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公开(公告)号：US08084324B2
公开(公告)日：2011-12-27
申请号：US12720062
申请日：2010-03-09
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/4763
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/0433 , G11C16/0483 , G11C16/30 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, a third and a fourth control gate electrode layer, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture, a fifth and a sixth control gate electrode layer, and a third metallic silicide film; and a liner insulating film directly disposed on a first source and drain region of the memory cell transistor, a second source and drain region of the low voltage transistor, and a third source and drain region of the high voltage transistor.
摘要翻译： 非易失性半导体存储器包括：存储单元晶体管，包括形成在第一隧道绝缘膜上的第一浮栅电极层，第一栅间绝缘膜，第一和第二控制栅极电极层和第一金属硅化物膜; 包括形成在高压栅极绝缘膜上的高电压栅极电极层，具有孔径的第二栅极间绝缘膜，第三和第四控制栅极电极层和第二金属硅化物膜的高压晶体管; 包括形成在第二隧道绝缘膜上的第二浮栅电极层，具有孔的第三栅间绝缘膜，第五和第六控制栅极电极层和第三金属硅化物膜的低压晶体管; 以及直接设置在存储单元晶体管的第一源极和漏极区域，低压晶体管的第二源极和漏极区域以及高压晶体管的第三源极和漏极区域中的衬垫绝缘膜。
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公开(公告)号：US07919823B2
公开(公告)日：2011-04-05
申请号：US12716322
申请日：2010-03-03
申请人： Atsuhiro Sato , Kikuko Sugimae , Masayuki Ichige
发明人： Atsuhiro Sato , Kikuko Sugimae , Masayuki Ichige
CPC分类号： H01L27/11519 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A semiconductor integrated circuit device includes a cell well, a memory cell array formed on the cell well and having a memory cell area and cell well contact area, first wiring bodies arranged in the memory cell area, and second wiring bodies arranged in the cell well contact area. The layout pattern of the second wiring bodies is the same as the layout pattern of the first wiring bodies. The cell well contact area comprises cell well contacts that have the same dopant type as the cell well and that function as source/drain regions of dummy transistors formed in the cell well contact area.
摘要翻译： 一种半导体集成电路器件，包括：单元阱，形成在单元阱上的存储单元阵列，具有存储单元区域和单元阱接触区域，布置在存储单元区域中的第一布线体以及布置在单元阱中的第二布线体 接触面积 第二布线体的布局图案与第一布线体的布局图形相同。 电池阱接触区域包括具有与电池阱相同的掺杂剂类型的电池阱触点，并且用作在电池阱接触区域中形成的虚拟晶体管的源极/漏极区域。
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公开(公告)号：US20070109848A1
公开(公告)日：2007-05-17
申请号：US11553661
申请日：2006-10-27
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/0433 , G11C16/0483 , G11C16/30 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, a third and a fourth control gate electrode layer, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture, a fifth and a sixth control gate electrode layer, and a third metallic silicide film; and a liner insulating film directly disposed on a first source and drain region of the memory cell transistor, a second source and drain region of the low voltage transistor, and a third source and drain region of the high voltage transistor.
摘要翻译： 非易失性半导体存储器包括：存储单元晶体管，包括形成在第一隧道绝缘膜上的第一浮栅电极层，第一栅间绝缘膜，第一和第二控制栅极电极层和第一金属硅化物膜; 包括形成在高压栅极绝缘膜上的高电压栅极电极层，具有孔径的第二栅极间绝缘膜，第三和第四控制栅极电极层和第二金属硅化物膜的高压晶体管; 包括形成在第二隧道绝缘膜上的第二浮栅电极层，具有孔的第三栅间绝缘膜，第五和第六控制栅极电极层和第三金属硅化物膜的低压晶体管; 以及直接设置在存储单元晶体管的第一源极和漏极区域，低压晶体管的第二源极和漏极区域以及高压晶体管的第三源极和漏极区域中的衬垫绝缘膜。
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