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209 条记录 (耗时 0.051 秒)

    INTEGRATED CIRCUIT INTERCONNECT STRUCTURE
    21.
    发明申请
    INTEGRATED CIRCUIT INTERCONNECT STRUCTURE 有权
    集成电路互连结构

    公开(公告)号：US20110254168A1

    公开(公告)日：2011-10-20

    申请号：US12760594

    申请日：2010-04-15

    申请人： Hanyi Ding ,  Ronald G. Filippi ,  Jong-Ru Guo ,  Ping-Chuan Wang

    发明人： Hanyi Ding ,  Ronald G. Filippi ,  Jong-Ru Guo ,  Ping-Chuan Wang

    IPC分类号： H01L23/522 ,  H01L21/768 ,  G06F17/50

    CPC分类号： H01L23/528 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.

    摘要翻译： 一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中的缓冲金属段，并在其相对端耦合到第一通孔。 缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。 缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。

    Method of and structure for recovering gain in a bipolar transistor
    23.
    发明授权
    Method of and structure for recovering gain in a bipolar transistor 有权
    双极晶体管中恢复增益的方法和结构

    公开(公告)号：US07961032B1

    公开(公告)日：2011-06-14

    申请号：US12627282

    申请日：2009-11-30

    申请人： Zhijian Yang ,  Ping-Chuan Wang ,  Kai Di Feng

    发明人： Zhijian Yang ,  Ping-Chuan Wang ,  Kai Di Feng

    IPC分类号： H03K17/60

    CPC分类号： H03F1/302

    摘要： A method of recovering gain in a bipolar transistor includes: providing a bipolar transistor including an emitter, a collector, and a base disposed between junctions at the emitter and the collector; reverse biasing the junction disposed between the emitter and the base with an operational voltage and for an operational time period, so that a current gain β of the transistor is degraded; idling the transistor, and generating a repair current Ibr into the base, while forward biasing the junction disposed between the emitter and the base with a first repair voltage (VEBR), and while at least partly simultaneously reverse biasing the junction disposed between the collector and the base with a second repair voltage (VCBR), for a repair time period (TR), so that the gain is at least party recovered; wherein VEBR, VCBR and TR have the proportional relationship: TR ∝ (Δβ)2×exp [1/(Tam+Rth×le×VCER)], VCER=VBER+VCBR, and le=β×Ibr, β is the normal current gain of the transistor, Δβ is the target recovery gain of the transistor in percentage, Tam is the ambient temperature in degrees K, Ibr is the repair current to the base in μamps, Rth is the self-heating thermal resistance of the transistor in K/W, TR is in seconds. The invention further includes structures for implementing the method.

    摘要翻译： 一种在双极晶体管中恢复增益的方法，包括：提供一个包括发射极，集电极和设置在发射极和集电极之间的结之间的基极的双极晶体管; 使用工作电压和工作时间周期反向偏置设置在发射极和基极之间的结，使得电流增益＆bgr; 的晶体管劣化; 使晶体管怠速，并产生修复电流Ibr到基极，同时以第一修复电压（VEBR）向前偏置设置在发射极和基极之间的结，并且至少部分地同时反向偏置设置在集电极和 具有第二修复电压（VCBR）的基座，用于修复时间段（TR），使得增益至少被回收; 其中VEBR，VCBR和TR具有比例关系：TRα（＆Dgr;＆bgr;）2×exp [1 /（Tam + Rth×le×VCER）]，VCER = VBER + VCBR，和le =＆bgr;×Ibr， ＆bgr 是晶体管的正常电流增益，＆Dgr; 是晶体管的目标恢复增益百分比，谭是以K为单位的环境温度，Ibr是以μ为单位的基极修复电流，Rth是晶体管的自热热阻，K / W，TR在 秒。 本发明还包括用于实现该方法的结构。

    Test Structure for Determination of TSV Depth
    25.
    发明申请
    Test Structure for Determination of TSV Depth 有权
    测定TSV深度的测试结构

    公开(公告)号：US20110073858A1

    公开(公告)日：2011-03-31

    申请号：US12566726

    申请日：2009-09-25

    申请人： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

    发明人： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

    IPC分类号： H01L23/48 ,  H01L21/66

    CPC分类号： H01L22/34 ,  H01L21/76898

    摘要： A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel.

    摘要翻译： 半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。 确定半导体芯片中的硅通孔（TSV）的深度的方法包括将第一TSV蚀刻到半导体芯片中; 形成第一通道，所述第一通道包括第一TSV，电连接到第一TSV的第一触点和第二触点; 将电流源连接到第二触点; 确定跨越第一通道的电阻; 以及基于所述第一通道的电阻确定所述第一TSV的深度。

    In-line depth measurement for thru silicon via
    26.
    发明授权
    In-line depth measurement for thru silicon via 有权
    通过硅通孔的在线深度测量

    公开(公告)号：US07904273B2

    公开(公告)日：2011-03-08

    申请号：US12371724

    申请日：2009-02-16

    申请人： Qizhi Liu ,  Ping-Chuan Wang ,  Kimball M. Watson ,  Zhijian J. Yang

    发明人： Qizhi Liu ,  Ping-Chuan Wang ,  Kimball M. Watson ,  Zhijian J. Yang

    IPC分类号： G06F19/00

    CPC分类号： H01L22/34 ,  H01L2924/3011

    摘要： A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication.

    摘要翻译： 在线半导体制造期间，用于测量晶片上的半导体器件区域中的硅硅通孔（TSV）的深度的系统，方法和装置包括在衬底中具有长度和宽度尺寸的电阻测量沟槽结构， 设置在电阻测量沟槽结构的相对侧的衬底的表面上的欧姆接触，以及具有未知深度的半导体器件区域中的未填充的TSV结构。 测试电路与欧姆接触件接触并测量它们之间的电阻，连接到测试电路的处理器基于电阻测量来计算沟槽结构的深度和未填充的TSV结构。 在制造期间同时产生电阻测量沟槽结构和未填充TSV。

    Structures including integrated circuits for reducing electromigration effect
    27.
    发明授权
    Structures including integrated circuits for reducing electromigration effect 有权
    包括用于降低电迁移效应的集成电路的结构

    公开(公告)号：US07861204B2

    公开(公告)日：2010-12-28

    申请号：US11960853

    申请日：2007-12-20

    申请人： Anthony Kendall Stamper ,  Timothy Dooling Sullivan ,  Ping-Chuan Wang

    发明人： Anthony Kendall Stamper ,  Timothy Dooling Sullivan ,  Ping-Chuan Wang

    IPC分类号： G06F17/50

    CPC分类号： H01L23/53223 ,  H01L23/528 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A design structure including an integrated circuit for reducing the electromigration effect. The IC includes a substrate and a power transistor which has first and second source/drain regions. The IC further includes first, second, and third electrically conductive line segments being (i) directly above the first source/drain region and (ii) electrically coupled to the first source/drain region through first contact regions and second contact regions, respectively. The first and second electrically conductive line segments (i) reside in a first interconnect layer of the integrated circuit and (ii) run in the reference direction. The IC further includes an electrically conductive line being (i) directly above the first source/drain region, (ii) electrically coupled to the first and second electrically conductive line segments through a first via and a second via, respectively, (iii) resides in a second interconnect layer of the integrated circuit, and (iv) runs in the reference direction.

    摘要翻译： 一种设计结构，包括用于降低电迁移效应的集成电路。 IC包括具有第一和第二源/漏区的衬底和功率晶体管。 IC还包括第一，第二和第三导电线段，其直接在第一源极/漏极区域的上方，以及（ii）分别通过第一接触区域和第二接触区域电耦合到第一源极/漏极区域。 第一和第二导电线段（i）驻留在集成电路的第一互连层中，并且（ii）沿参考方向延伸。 IC还包括导电线，其是（i）直接在第一源极/漏极区域上方，（ii）分别通过第一通孔和第二通孔电耦合到第一和第二导电线段，（iii）驻留 在集成电路的第二互连层中，以及（iv）在参考方向上延伸。

    PROGRAMMABLE PN ANTI-FUSE
    28.
    发明申请
    PROGRAMMABLE PN ANTI-FUSE 有权
    可编程PN防熔丝

    公开(公告)号：US20100295132A1

    公开(公告)日：2010-11-25

    申请号：US12698302

    申请日：2010-02-02

    申请人： Ping-Chuan Wang ,  Robert C. Wong ,  Haining S. Yang

    发明人： Ping-Chuan Wang ,  Robert C. Wong ,  Haining S. Yang

    IPC分类号： H01L27/06 ,  H01L21/8234 ,  H01L21/326

    CPC分类号： H01L27/0727 ,  H01L23/5252 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Structure and method for providing a programmable anti-fuse in a FET structure. A method of forming the programmable anti-fuse includes: providing a p− substrate with an n+ gate stack; implanting an n+ source region and an n+ drain region in the p− substrate; forming a resist mask over the n+ drain region, while leaving the n+ source region exposed; etching the n+ source region to form a recess in the n+ source region; and growing a p+ epitaxial silicon germanium layer in the recess in the n+ source region to form a pn junction that acts as a programmable diode or anti-fuse.

    摘要翻译： 在FET结构中提供可编程反熔丝的结构和方法。 形成可编程反熔丝的方法包括：提供具有n +栅极叠层的p衬底; 在p衬底中注入n +源极区域和n +漏极区域; 在n +漏极区域上形成抗蚀剂掩模，同时使n +源极区域露出; 蚀刻n +源极区域以在n +源极区域中形成凹陷; 以及在n +源极区的凹槽中生长p +外延硅锗层以形成用作可编程二极管或反熔丝的pn结。

    THREE-DIMENSIONAL CHIP-STACK SYNCHRONIZATION
    29.
    发明申请
    THREE-DIMENSIONAL CHIP-STACK SYNCHRONIZATION 有权
    三维芯片堆叠同步

    公开(公告)号：US20100277210A1

    公开(公告)日：2010-11-04

    申请号：US12432801

    申请日：2009-04-30

    申请人： Ping-Chuan Wang ,  Anthony R. Bonaccio ,  Jong-Ru Guo ,  Louis Lu-Chen Hsu

    发明人： Ping-Chuan Wang ,  Anthony R. Bonaccio ,  Jong-Ru Guo ,  Louis Lu-Chen Hsu

    IPC分类号： H03L7/06

    CPC分类号： H03L7/099 ,  H03L7/18 ,  H03L7/22

    摘要： a central reference clock is placed in a substantially middle chip of a 3-D chip-stack. The central reference clock is distributed to each child chip of the 3-D chip-stack, so that a plurality of clocks is generated for each individual chip in the 3-D-stack in a synchronous manner. A predetermined number of through-silicon-vias and on-chip wires are employed to form a delay element for each slave clock, ensuring that the clock generated for each child chip is substantially synchronized. Optionally, an on-chip clock trimming circuit is embedded for further precision tuning to eliminate local clock skews.

    摘要翻译： 中心参考时钟被放置在3-D芯片堆叠的基本上中间的芯片中。 中心参考时钟被分配给3-D芯片组的每个子芯片，从而以同步的方式为3-D堆叠中的每个芯片生成多个时钟。 采用预定数量的通硅通孔和片上导线来形成每个从时钟的延迟元件，确保为每个子芯片生成的时钟基本上同步。 可选地，嵌入式片上时钟微调电路用于进一步精确调谐以消除本地时钟偏移。