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公开(公告)号：US5170375A
公开(公告)日：1992-12-08
申请号：US782798
申请日：1991-09-18
申请人： Hans-Juergen Mattausch , Bernhard Hoppe , Gerd Neuendorf , Doris Schmitt-Landsiedel , Hans-Joerg Pfleiderer , Maria Wurm
发明人： Hans-Juergen Mattausch , Bernhard Hoppe , Gerd Neuendorf , Doris Schmitt-Landsiedel , Hans-Joerg Pfleiderer , Maria Wurm
IPC分类号： G11C5/02 , G11C8/12 , G11C11/417 , G11C11/418 , G11C11/419
CPC分类号： G11C5/025 , G11C11/417 , G11C11/418 , G11C11/419 , G11C8/12
摘要： A static memory is constructed in a plurality of hierarchy levels. Beneficial realization possibilities are set forth with respect to the surface utilization for the drive and read-out circuits in the second hierarchy level which are especially critical. Memory cells that supply a strong cell signal are advantageously utilized so that a low expense is needed in the read circuit. By displacing periphery circuits into higher hierarchy levels, a short access time and a reduced surface requirement arise.
摘要翻译： 静态存储器被构造在多个层级中。 关于特别关键的第二层次的驱动和读出电路的表面利用率，阐述了有益的实现可能性。 有利地利用提供强信元信号的存储单元，从而在读电路中需要低成本。 通过将外围电路移位到更高级别的层次，出现短的访问时间和减小的表面要求。
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22.发明授权Circuit configuration for forming a MOS capacitor with a lower voltage dependence and a lower area requirement 失效用于形成具有较低电压依赖性和较低面积要求的MOS电容器的电路配置公开(公告)号：US06700149B2
公开(公告)日：2004-03-02
申请号：US10113421
申请日：2002-04-01
IPC分类号： H01L27088
CPC分类号： H01L27/0805 , H01L29/94
摘要： A circuit configuration for providing a capacitance includes short-channel MOS transistors that are reverse-connected in series or in parallel, and that have the same channel type. When the short-channel MOS transistors are operated exclusively in the depletion mode in the required voltage range, the useful capacitance is increased, because of intrinsic capacitances, as compared with circuit configurations having conventional long-channel MOS transistors. These circuits greatly reduce the area taken up and reduce the costs.
摘要翻译： 用于提供电容的电路配置包括串联或并联反向并且具有相同通道类型的短沟道MOS晶体管。 当短沟道MOS晶体管仅在所需电压范围内的耗尽模式下工作时，与具有常规长沟道MOS晶体管的电路配置相比，由于固有电容，有用电容增加。 这些电路大大减少了占用的面积并降低了成本。
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23.发明授权公开(公告)号：US06323728B1
公开(公告)日：2001-11-27
申请号：US09655285
申请日：2000-09-05
IPC分类号： H03D100
CPC分类号： G06K19/0723
摘要： A data carrier includes at least one coil for the contactless reception of amplitude-modulated signals. A rectifier circuit is connected downstream of the coil. A circuit configuration processes and/or stores data. A supply-voltage control circuit is connected in parallel with the circuit configuration. A current measuring device acts as an amplitude demodulator and is disposed between the coil and the voltage-supply control circuit.
摘要翻译： 数据载体包括至少一个线圈，用于非接触式地接收幅度调制信号。 整流电路连接在线圈的下游。 电路配置处理和/或存储数据。 电源电压控制电路与电路配置并联连接。 电流测量装置用作幅度解调器，并设置在线圈和电源控制电路之间。
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公开(公告)号：US5831892A
公开(公告)日：1998-11-03
申请号：US904373
申请日：1997-08-01
CPC分类号： G11C17/126 , G11C11/56 , G11C11/5692 , G11C16/0491 , G11C2211/5631 , G11C2211/5634 , G11C7/1006
摘要： A matrix memory with improved virtual ground architecture and evaluation circuit from which the informational content of two neighboring memory cells can be simultaneously read at a bit line during a read event. The memory cells with information "0" are realized, for example, by a respective field effect transistor with low threshold voltage. Every bit line provided for the readout is connected to the drain terminals of two neighboring field effect transistors in the same row. The source terminals are applied to one of two potentials that differ from one another. Depending upon which of the field effect transistors is conductive upon selection of the pertinent word line, different resultant potentials are obtained on the bit line. Such potentials are then converted in the evaluation circuit into binary signals that represent the read information.
摘要翻译： 具有改进的虚拟地面架构和评估电路的矩阵存储器，可以在读取事件期间在位线上同时读取两个相邻存储器单元的信息内容。 具有信息“0”的存储单元例如由具有低阈值电压的各自的场效应晶体管实现。 为读出提供的每个位线连接到同一行中的两个相邻场效应晶体管的漏极端子。 源端子被施加到彼此不同的两个电位之一。 取决于在选择相关字线时场效应晶体管是导通的，在位线上获得不同的合成电位。 然后将这些电位在评估电路中转换为表示读取信息的二进制信号。
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公开(公告)号：US5040146A
公开(公告)日：1991-08-13
申请号：US491201
申请日：1990-03-09
申请人： Hans-Juergen Mattausch , Bernhard Hoppe , Gerd Neuendorf , Doris Schmitt-Landsiedel , Hans-Joerg Pfleiderer , Maria Wurm
发明人： Hans-Juergen Mattausch , Bernhard Hoppe , Gerd Neuendorf , Doris Schmitt-Landsiedel , Hans-Joerg Pfleiderer , Maria Wurm
IPC分类号： G11C8/16 , G11C11/412
CPC分类号： G11C8/16 , G11C11/412
摘要： Memory cells are disclosed that avoid the utilization of analog circuits in the memory peripheral circuits when they are utilized in static memory modules and that intended to enhance the disturbed reliability when confronted by technology modifications and parameter fluctuations. Write-in thereby occurs from a write data line via a write selection transistor and read-out occurs via a read selection transistor onto a read data line. A second inverter formed of two field effect transistors serves as a feedback element in order to statically maintain the cell information. Due to an implemented asymmetry in the dimensioning between the first and second inverters, the memory cell is significantly less susceptible to information loss upon read-out when compared to a heretofore known memory cell. A precharging of the read data line is not required with these memory cells.
摘要翻译： 公开了存储器单元，当它们被用于静态存储器模块中时，避免在存储器外围电路中利用模拟电路，并且旨在在面临技术修改和参数波动时提高干扰的可靠性。 通过写入选择晶体管从写入数据线发生写入，并且通过读取选择晶体管将读出发生到读取数据线上。 由两个场效应晶体管形成的第二反相器用作反馈元件，以便静态地维持单元信息。 由于在第一和第二逆变器之间的尺寸确定方面的不对称性，当与先前已知的存储器单元相比时，存储器单元在读出时显着地较不易于信息丢失。 这些存储单元不需要读取数据线的预充电。
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公开(公告)号：US20090115468A1
公开(公告)日：2009-05-07
申请号：US12090165
申请日：2006-09-28
申请人： Joerg Berthold , Matthias Eireiner , Georg Georgakos , Stephan Henzler , Christian Pacha , Doris Schmitt-Landsiedel
发明人： Joerg Berthold , Matthias Eireiner , Georg Georgakos , Stephan Henzler , Christian Pacha , Doris Schmitt-Landsiedel
IPC分类号： H03L7/00
CPC分类号： H03K3/356156
摘要： An integrated circuit, comprising a first data retention element configured to retain the data, the first data retention element having a first setup time, and a second data retention element configured to retain the data, the second data retention element having a second setup time, the second data retention element further having a data input. The second data retention element is connected in parallel with the first data retention element, and the second data retention element is configurable via the data input such that the second setup time is longer than the first setup time.
摘要翻译： 一种集成电路，包括被配置为保留数据的第一数据保持元件，具有第一建立时间的第一数据保持元件和被配置为保留数据的第二数据保持元件，第二数据保持元件具有第二建立时间， 所述第二数据保留元件还具有数据输入。 第二数据保持元件与第一数据保持元件并联连接，并且第二数据保持元件可经由数据输入配置，使得第二建立时间比第一建立时间长。
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公开(公告)号：US06181183B2
公开(公告)日：2001-01-30
申请号：US09269047
申请日：1999-03-18
IPC分类号： H03K513
CPC分类号： H03K5/133
摘要： A circuit with a delay stage formed by an invertor having high-impedance transistors and, connected in series therewith, an invertor having low-impedance transistors MOS capacitors are provided between the gates of the transistors of the low-impedance invertor and the output of the delay stage. By means of this circuit, delay stages with steep edges can be realized with comparatively less outlay on components.
摘要翻译： 具有由具有高阻抗晶体管的反相器形成的延迟级的电路设置在低阻抗反相器的晶体管的栅极和 延迟阶段 通过该电路，可以实现具有陡峭边缘的延迟级，而在组件上的相对较少的支出。
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28.发明授权Digital/analog converter using a floating gate MOS neuron transistor with capacitive coupling 失效数字/模拟转换器采用具有电容耦合的浮栅MOS神经元晶体管
公开(公告)号：US6037885A
公开(公告)日：2000-03-14
申请号：US7252
申请日：1998-01-14
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H03M1/66 , H03M1/74 , H03M1/80 , H03M1/00
CPC分类号： H03M1/802
摘要： A digital/analog converter has a neuron MOS transistor, a maintenance circuit which keeps the drain potential of the neuron MOS transistor constant, and a current source. A linear dynamic range in terms of large signal is possible, so that converters having a larger input word size than, for example, only two bits can be realized in a simple way with low dissipated power. Such converters are of significance particularly for ULSI circuits.
摘要翻译： 数字/模拟转换器具有神经元MOS晶体管，保持神经元MOS晶体管的漏极电位恒定的维护电路和电流源。 在大信号方面的线性动态范围是可能的，因此具有比例如仅两位更大的输入字大小的转换器可以以低耗散功率以简单的方式实现。 这种转换器对于ULSI电路尤其重要。
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公开(公告)号：US4661831A
公开(公告)日：1987-04-28
申请号：US633599
申请日：1984-07-23
IPC分类号： G11C11/412 , H01L21/8249 , H01L27/06 , H01L27/10 , H03K3/356 , H01L27/02 , G11C11/34 , H01L27/12
CPC分类号： H03K3/356017
摘要： An integrated RS flip-flop circuit comprises two cross-coupled inverters which respectively consist of a field effect transistor and a resistor connected in series. Each field effect transistor is connected to an additional logic element whose control input represents the R or the S input, respectively. Realization of a flip-flop circuit on the smallest possible semiconductor is achieved by designing the additional logic elements as hot electron transistors, each of which is combined with one of the field effect transistors to form a common component which assumes two transistor functions but only requires the area of one field effect transistor. The invention is particularly useful in VLSI circuits.
摘要翻译： 集成RS触发器电路包括两个交叉耦合的反相器，它们分别由场效应晶体管和串联的电阻组成。 每个场效应晶体管分别连接到控制输入表示R或S输入的附加逻辑元件。 通过将附加逻辑元件设计为热电子晶体管来实现最小可能的半导体上的触发器电路的实现，其中每一个都与场效应晶体管中的一个组合，以形成假设两个晶体管功能但仅需要 一个场效应晶体管的面积。 本发明在VLSI电路中特别有用。
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公开(公告)号：US4626887A
公开(公告)日：1986-12-02
申请号：US637026
申请日：1984-08-02
IPC分类号： G11C11/412 , H01L21/8249 , H01L27/06 , H01L27/10 , H01L29/76 , H01L27/02 , G11C11/34 , H01L29/80 , H01L49/02
CPC分类号： G11C11/412 , H01L29/7606
摘要： A static storage cell is formed of two cross-coupled inverters each containing a field effect transistor and a resistor element connected in series therewith. Each circuit node is thus connected via an additional logic element to a bit line allocated thereto. A storage cell is provided which is on as small as possible a semiconductor area and has a short access time. This is achieved by designing the additional logic elements as hot electron transistors which are respectively combined with one of the field effect transistors to form a common component which only requires the area of a field effect transistor. The cell is useful in VLSI semiconductor memories.
摘要翻译： 静态存储单元由两个交叉耦合的反相器形成，每个交流耦合反相器包含串联连接的场效应晶体管和电阻元件。 因此，每个电路节点经由附加逻辑元件连接到分配给它的位线。 提供一个尽可能小的半导体区域并具有短的访问时间的存储单元。 这通过将额外的逻辑元件设计为热电子晶体管来实现，该热电子晶体管分别与场效应晶体管之一组合以形成仅需要场效应晶体管的面积的公共分量。 该电池在VLSI半导体存储器中是有用的。
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