公开(公告)号：US6147918A

公开(公告)日：2000-11-14

申请号：US165190

申请日：1998-10-02

申请人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

发明人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

IPC分类号： G11C7/06 ,  G11C11/4091 ,  H01L27/108 ,  G11C7/02

CPC分类号： G11C7/065 ,  G11C11/4091 ,  H01L27/108

摘要： A dynamic semiconductor memory device is made up of a plurality of dynamic memory cells arrayed along a plurality of bit line pairs, and a plurality of dynamic sense amplifiers associated with the plurality of bit line pairs, each sense amplifier having a pair of MOS transistors connected to a corresponding pair of bit lines. In one embodiment, the first and second transistors of one of the sense amplifiers and the first and second transistors of another sense amplifier adjacent thereto are positioned within a region defined by two adjacent pairs of bit lines. Each of the bit line pairs has first and second bit lines extending in a first direction perpendicular to a second direction in which the source and drain regions are formed in the semiconductor substrate so that the transistors of the sense amplifiers are arranged one for every four bit lines in the second direction.

摘要翻译： 动态半导体存储器件由沿着多个位线对排列的多个动态存储器单元和与多个位线对相关联的多个动态读出放大器组成，每个读出放大器具有连接的一对MOS晶体管 到相应的一对位线。 在一个实施例中，读出放大器之一的第一和第二晶体管和与其相邻的另一个读出放大器的第一和第二晶体管位于由两个相邻的位线对限定的区域内。 每个位线对具有在与第二方向垂直的第一方向上延伸的第一和第二位线，其中源极和漏极区域形成在半导体衬底中，使得读出放大器的晶体管每四位排列一个 线在第二个方向。

公开(公告)号：US5953246A

公开(公告)日：1999-09-14

申请号：US845035

申请日：1997-04-21

申请人： Daisaburo Takashima ,  Yukihito Oowaki

发明人： Daisaburo Takashima ,  Yukihito Oowaki

IPC分类号： G11C11/405 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4094 ,  G11C14/00 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  G11C11/24

CPC分类号： G11C11/4094 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4085

摘要： A semiconductor memory device comprises a plurality of word lines, a plurality of bit lines intersecting the word lines, and memory cells selectively arranged at intersections of the word lines and the bit lines, and each consisting of a transistor and a capacitor, the transistor having a gate thereof connected to a corresponding one of the word lines, a drain thereof connected to a corresponding one of the bit lines, and a source thereof connected to an end of the capacitor and serving as a memory node, the capacitor having another end thereof connected to a plate electrode. In the semiconductor memory device, in an active mode assumed when a power supply is in an on state, that transistor of a memory cell which is connected to a selected one of the word lines is turned on, and those transistors of the other memory cells which are connected to non-selected word lines are in an off state. Further, in a standby mode assumed when the power supply is in the on state, when the power supply is in an off state, and when the power supply is turned on and off, the transistors of all the memory cells are in an off state.

摘要翻译： 半导体存储器件包括多个字线，与字线相交的多个位线，以及选择性地布置在字线和位线的交点处的存储器单元，并且每个由晶体管和电容器组成，所述晶体管具有 其栅极连接到对应的一条字线，其漏极连接到对应的一条位线，以及连接到电容器的端部并用作存储器节点的源极，该电容器的另一端 连接到平板电极。 在半导体存储器件中，当电源处于导通状态时，处于主动模式中，连接到所选择的一个字线的存储单元的该晶体管导通，并且其它存储单元的那些晶体管 连接到未选择的字线的是处于关闭状态。 此外，在电源处于接通状态时所假设的待机模式下，当电源处于断开状态时，当电源接通和断开时，所有存储单元的晶体管处于断开状态 。

公开(公告)号：US5870339A

公开(公告)日：1999-02-09

申请号：US742924

申请日：1996-11-01

申请人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

发明人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

IPC分类号： G11C11/407 ,  G11C7/06 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C16/04

CPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C7/065

摘要： A MOS dynamic random access memory includes a plurality of pairs of bit lines, and word lines transverse to the bit lines to define cross points, at which an array of memory cells are arranged. Each cell has a storage capacitor and a transfer gate MOS transistor having a gate electrode coupled to a word line and being connected between the capacitor and a bit line. Sense amplifier circuits are connected to the bit line pairs, and have a first and a second common source line. A decoder and a word line driver are connected to the word lines. A MOS transistor is connected between the power supply voltage and the first common source line, for selectively supplying it with a first voltage which potentially defines a high-level voltage for the bit line pairs. A voltage generator is connected through a MOS transistor to the second common source line, for generating a second voltage which potentially defines a low-level voltage for the bit line pairs, and which is selectively supplied to the second common source line. The second voltage is greater in potential than the ground potential, which is employed as a source voltage.

公开(公告)号：US5761109A

公开(公告)日：1998-06-02

申请号：US614537

申请日：1996-03-13

申请人： Daisaburo Takashima ,  Tsuneo Inaba ,  Yukihito Oowaki ,  Takashi Ohsawa ,  Shinichiro Shiratake

发明人： Daisaburo Takashima ,  Tsuneo Inaba ,  Yukihito Oowaki ,  Takashi Ohsawa ,  Shinichiro Shiratake

IPC分类号： G11C11/409 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C5/06

CPC分类号： G11C11/4097

摘要： A dynamic semiconductor memory device according to the present invention comprises at least first and second memory cell arrays having a plurality of memory cells selectively arranged at respective intersections of a plurality of word lines and a plurality of bit lines, a first sense amplifier section connected at an end of the first cell array to a plurality of bit line pairs formed by part of the plurality of bit lines of the first cell array, the plurality of bit line pairs having a folded bit line configuration, a second sense amplifier section connected to sets of bit line pairs, each formed by one of the remaining bit lines of the first cell array and one of part of the plurality of bit lines of the second cell array, the plurality of bit line pairs having an open bit line configuration, and a correction circuit for correcting the level of ease for reading data "0" and that of reading data "1".

摘要翻译： 根据本发明的动态半导体存储器件包括至少第一和第二存储器单元阵列，其具有选择性地布置在多个字线和多个位线的各个交点处的多个存储器单元，第一读出放大器部分连接在 第一单元阵列的一端到由第一单元阵列的多个位线的一部分形成的多个位线对，多个位线对具有折叠位线配置，第二读出放大器部分连接到组 的位线对，每个位线对由第一单元阵列的剩余位线之一和第二单元阵列的多个位线的一部分之一形成，多个位线对具有打开的位线配置，以及 用于校正读取数据“0”的容易程度的校正电路和读取数据“1”的校正电路。

公开(公告)号：US06690047B2

公开(公告)日：2004-02-10

申请号：US10132175

申请日：2002-04-26

申请人： Yukihito Oowaki ,  Mizuki Ono ,  Mitsuhiro Noguchi ,  Daisaburo Takashima ,  Akira Nishiyama

发明人： Yukihito Oowaki ,  Mizuki Ono ,  Mitsuhiro Noguchi ,  Daisaburo Takashima ,  Akira Nishiyama

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78

摘要： In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer than the channel plane than the interface between a gate insulator film provided on the upper side of the channel plane and the gate electrode. In this transistor, a groove is selectively formed in the surface of the semiconductor substrate, and a polycrystalline silicon deposited in the groove may be used as a mask to form impurity diffusion layers serving as source/drain regions to laminate and form a gate insulator film of a high dielectric film and a gate electrode. Alternatively, the polycrystalline silicon may be selectively formed to be used as a mask to elevate and form the impurity diffusion layer to laminate and form the gate insulator film and the gate electrode. Thus, it is possible to achieve both of the reduction of the resistance of the S/D diffusion layers and the reduction of the gate parasitic capacitance.

摘要翻译： 在MIS晶体管中，形成在半导体基板1上的源极/漏极区域（S / D扩散层）的上表面布置成比半导体衬底上的沟道平面更靠近栅电极，源极/漏极区域的顶表面 漏区比布置在沟道平面上侧的栅极绝缘膜与栅电极之间的界面更靠近沟道平面。 在该晶体管中，在半导体衬底的表面中选择性地形成沟槽，并且可以将沉积在沟槽中的多晶硅用作掩模，以形成用作源极/漏极区域的杂质扩散层，以层压并形成栅极绝缘膜 的高介电膜和栅电极。 或者，可以选择性地形成多晶硅以用作掩模以升高和形成杂质扩散层以层压并形成栅极绝缘膜和栅电极。 因此，可以实现S / D扩散层的电阻的降低和栅极寄生电容的降低。

公开(公告)号：US5859805A

公开(公告)日：1999-01-12

申请号：US832818

申请日：1997-04-04

申请人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

发明人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

IPC分类号： G11C7/06 ,  G11C11/4091 ,  H01L27/108 ,  G11C5/02

CPC分类号： G11C7/065 ,  G11C11/4091 ,  H01L27/108

摘要： A dynamic semiconductor memory device is made up of a plurality of dynamic memory cells arrayed along a plurality of bit line pairs, and a plurality of dynamic sense amplifiers associated with the plurality of bit line pairs, each sense amplifier having a pair of MOS transistors connected to a corresponding pair of bit lines. In one embodiment, the first and second transistors of one of the sense amplifiers and the first and second transistors of another sense amplifier adjacent thereto are positioned within a region defined by two adjacent pairs of bit lines. Each of the bit line pairs has first and second bit lines extending in a first direction perpendicular to a second direction in which the source and drain regions are formed in the semiconductor substrate so that the transistors of the sense amplifiers are arranged one for every four bit lines in the second direction.

公开(公告)号：US5644525A

公开(公告)日：1997-07-01

申请号：US272284

申请日：1994-07-08

申请人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

发明人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

IPC分类号： G11C7/06 ,  G11C11/4091 ,  H01L27/108 ,  G11C5/02 ,  G11C11/407 ,  G11C11/413

CPC分类号： G11C7/065 ,  G11C11/4091 ,  H01L27/108

摘要： A dynamic semiconductor memory device is made up of a plurality of dynamic memory cells arrayed along a plurality of bit line pairs, and a plurality of dynamic sense amplifiers associated with the plurality of bit line pairs, each sense amplifier having a pair of MOS transistors connected to a corresponding pair of bit lines. In one embodiment, the first and second transistors of one of the sense amplifiers and the first and second transistors of another sense amplifier adjacent thereto are positioned within a region defined by two adjacent pairs of bit lines. Each of the bit line pairs has first and second bit lines extending in a first direction perpendicular to a second direction in which the source and drain regions are formed in the semiconductor substrate so that the transistors of the sense amplifiers are arranged one for every four bit lines in the second direction.

摘要翻译： 动态半导体存储器件由沿着多个位线对排列的多个动态存储器单元和与多个位线对相关联的多个动态读出放大器组成，每个读出放大器具有连接的一对MOS晶体管 到相应的一对位线。 在一个实施例中，读出放大器之一的第一和第二晶体管和与其相邻的另一个读出放大器的第一和第二晶体管位于由两个相邻的位线对限定的区域内。 每个位线对具有在与第二方向垂直的第一方向上延伸的第一和第二位线，其中源极和漏极区域形成在半导体衬底中，使得读出放大器的晶体管每四位排列一个 线在第二个方向。

公开(公告)号：US5638329A

公开(公告)日：1997-06-10

申请号：US420079

申请日：1995-04-11

申请人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

发明人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

IPC分类号： G11C11/407 ,  G11C7/06 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C7/065

摘要： A MOS dynamic random access memory includes a plurality of pairs of bit lines, and word lines transverse to the bit lines to define cross points, at which an array of memory cells are arranged. Each cell has a storage capacitor and a transfer gate MOS transistor having a gate electrode coupled to a word line and being connected between the capacitor and a bit line. Sense amplifier circuits are connected to the bit line pairs, and have a first and a second common source line. A decoder and a word line driver are connected to the word lines. AMOS transistor is connected between the power supply voltage and the first common source line, for selectively supplying it with a first voltage which potentially defines a high-level voltage for the bit line pairs. A voltage generator is connected through a MOS transistor to the second common source line, for generating a second voltage which potentially defines a low-level voltage for the bit line pairs, and which is selectively supplied to the second common source line. The second voltage is greater in potential than the ground potential, which is employed as a source voltage.

摘要翻译： MOS动态随机存取存储器包括多对位线和横向于位线的字线以定义交叉点，存储器单元阵列布置在该交叉点处。 每个单元具有存储电容器和传输门MOS晶体管，其具有耦合到字线并连接在电容器和位线之间的栅电极。 感测放大器电路连接到位线对，并且具有第一和第二公共源极线。 解码器和字线驱动器连接到字线。 AMOS晶体管连接在电源电压和第一公共源极线之间，用于选择性地向其提供潜在地限定位线对的高电平电压的第一电压。 电压发生器通过MOS晶体管连接到第二公共源极线，用于产生可能限定位线对的低电平电压的第二电压，并且被选择性地提供给第二公共源极线。 第二电压的电位比接地电位大，用作电源电压。

公开(公告)号：US5426604A

公开(公告)日：1995-06-20

申请号：US197409

申请日：1994-02-16

申请人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

发明人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

IPC分类号： G11C11/407 ,  G11C7/06 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C11/24

CPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C7/065

摘要： A MOS dynamic random access memory includes a plurality of pairs of bit lines, and word lines transverse to the bit lines to define cross points, at which an array of memory cells are arranged. Each cell has a storage capacitor and a transfer gate MOS transistor having a gate electrode coupled to a word line and being connected between the capacitor and a bit line. Sense amplifier circuits are connected to the bit line pairs, and have a first and a second common source line. A decoder and a word line driver are connected to the word lines. A MOS transistor is connected between the power supply voltage and the first common source line, for selectively supplying it with a first voltage which potentially defines a high-level voltage for the bit line pairs. A voltage generator is connected through a MOS transistor to the second common source line, for generating a second voltage which potentially defines a low-level voltage for the bit line pairs, and which is selectively supplied to the second common source line. The second voltage is greater in potential than the ground potential, which is employed as a source voltage.

摘要翻译： MOS动态随机存取存储器包括多对位线和横向于位线的字线以定义交叉点，存储器单元阵列布置在该交叉点处。 每个单元具有存储电容器和传输门MOS晶体管，其具有耦合到字线并连接在电容器和位线之间的栅电极。 感测放大器电路连接到位线对，并且具有第一和第二公共源极线。 解码器和字线驱动器连接到字线。 MOS晶体管连接在电源电压和第一公共源极线之间，用于选择性地向其提供潜在地限定位线对的高电平电压的第一电压。 电压发生器通过MOS晶体管连接到第二公共源极线，用于产生可能限定位线对的低电平电压的第二电压，并且被选择性地提供给第二公共源极线。 第二电压的电位比接地电位大，用作电源电压。

公开(公告)号：US5144583A

公开(公告)日：1992-09-01

申请号：US461121

申请日：1990-01-04

申请人： Yukihito Oowaki ,  Kenji Tsuchida ,  Daisaburo Takashima

发明人： Yukihito Oowaki ,  Kenji Tsuchida ,  Daisaburo Takashima

IPC分类号： G11C11/4097 ,  H01L23/528 ,  H01L27/108

CPC分类号： H01L27/10805 ,  G11C11/4097 ,  H01L23/528 ,  H01L2924/0002

摘要： A dynamic random-access memory has bit-line pairs, word lines intersecting with the bit-line pairs, and memory cells arranged at the intersections of the bit-line pairs and the word lines, and sense amplifiers provided for the bit-line pairs, respectively. One of every two neighboring bit-line pairs is twisted at one portion, thus forming a twisted crossing section. The twisted crossing section is made of the parts of the gate electrodes of the transistors incorporated in the sense amplifier connected to the twisted bit-line pair. The bit-line pairs is twisted at a portion substantially middle with respect to the direction in which it extends, and the sensr amplifier associated with this bit-line pair is located at the twisted portion thereof.

摘要翻译： 动态随机存取存储器具有位线对，与位线对相交的字线和布置在位线对和字线的交点处的存储单元，以及为位线对提供的读出放大器 ， 分别。 每两个相邻位线对中的一个在一部分被扭曲，从而形成扭曲的交叉部分。 扭转交叉部分由连接到扭绞位线对的读出放大器中的晶体管的栅电极的部分构成。 位线对在相对于其延伸的方向大致中间的部分处扭曲，并且与该位线对相关联的感应放大器位于其扭曲部分处。