公开(公告)号：US11282851B2

公开(公告)日：2022-03-22

申请号：US16662073

申请日：2019-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong Kwon ,  Chanho Kim ,  Daeseok Byeon ,  Pansuk Kwak ,  Chiweon Yoon

IPC: H01L27/11573 ,  H01L23/522 ,  H01L27/1157 ,  H01L29/78 ,  H01L29/94 ,  H01L27/11582

Abstract: A non-volatile memory device includes a substrate, a memory cell string including a vertical channel structure and memory cells, a voltage generator including a first transistor and configured to provide various voltages to the memory cells, and a vertical capacitor structure. The vertical capacitor structure includes first and second active patterns apart from each other in a first horizontal direction, a first gate pattern located above a channel region between the first and second active patterns, a first gate insulating film between the first gate pattern and the substrate in a vertical direction, and capacitor electrodes each extending in the vertical direction. The first transistor includes a second gate pattern and a second gate insulating film between the second gate pattern and the substrate in the vertical direction. The first gate insulating film has a thickness greater than a thickness of the second gate insulating film in the vertical direction.

公开(公告)号：US11237983B2

公开(公告)日：2022-02-01

申请号：US16865580

申请日：2020-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyo Kim ,  Daeseok Byeon ,  Taehong Kwon ,  Chanho Kim ,  Taeyun Lee

IPC: G06F12/02 ,  G06F12/123 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G06F12/14

Abstract: A memory device includes; a memory area including a first memory area including first memory cells storing N-bit data and a second memory area including second memory cells storing M-bit data, where ‘M’ and ‘N’ are natural numbers and M is greater than N, and a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.

公开(公告)号：US11233042B2

公开(公告)日：2022-01-25

申请号：US16850493

申请日：2020-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Kim ,  Joo-Yong Park ,  Daeseok Byeon

IPC: H01L25/18 ,  H01L27/11573 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11582 ,  H01L49/02 ,  H01L27/11565 ,  H01L23/00 ,  H01L27/11575

Abstract: A three-dimensional semiconductor memory device, including a first chip and a second chip stacked on the first chip may be provided. The first chip may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, and second contact plugs, and a passive device on and electrically connected to the second contact plugs. The second chip may include a second substrate including a cell array region and a contact region, which vertically overlap the second peripheral circuit region and the first peripheral circuit region of the first chip, respectively. The second chip may further include gate electrodes, and cell contact plugs disposed on the contact region of the second substrate and on end portions of the gate electrodes. The first passive device may be vertically between the gate electrodes and the second contact plugs and may include a first contact line.

公开(公告)号：US11120843B2

公开(公告)日：2021-09-14

申请号：US16816476

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jooyong Park ,  Chanho Kim ,  Daeseok Byeon

IPC: H01L23/522 ,  G11C5/06 ,  G11C5/04 ,  G11C7/18

Abstract: A memory device includes a first semiconductor chip including a memory cell array disposed on a first substrate, and a first bonding metal on a first uppermost metal layer of the first semiconductor chip, and a second semiconductor chip including circuit devices disposed on a second substrate and a second bonding metal on a second uppermost metal layer of the second semiconductor chip, the circuit devices providing a peripheral circuit operating the memory cell array. The first and second semiconductor chips are electrically connected to each other by the first bonding metal and the second bonding metal in a bonding area. A routing wire electrically connected to the peripheral circuit is disposed in one or both of the first and second uppermost metal layers and is disposed in a non-bonding area in which the first and second semiconductor chips are not electrically connected to each other.

公开(公告)号：US11087844B2

公开(公告)日：2021-08-10

申请号：US16944312

申请日：2020-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chanho Kim ,  Kyunghwa Yun ,  Daeseok Byeon

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region. The memory cell region includes a plurality of word lines, a ground selection line in a layer on the word lines, a common source line in a layer on the ground selection line, a plurality of vertical pass transistors in the stair area, and a plurality of driving signal lines in the same layer as the common source line. The word lines form a stair shape in the stair area, and each of the vertical pass transistors is connected between a corresponding one of the word lines and a corresponding one of the driving signal lines.

公开(公告)号：US10381078B2

公开(公告)日：2019-08-13

申请号：US15992840

申请日：2018-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Kim ,  Dong-Kil Yun ,  Pansuk Kwak ,  Hongsoo Jeon

IPC: G11C14/00 ,  H01L27/11578 ,  H01L27/108 ,  H01L27/1157 ,  G11C11/4094 ,  G11C11/408 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C11/4091 ,  G11C16/04

Abstract: A semiconductor memory includes a first memory cell array in a first region of a substrate and a second memory cell array in a second region of the substrate. The first memory cell array includes cell strings, and each cell string includes non-volatile memory cells stacked in a direction perpendicular to the substrate. The second memory cell array includes volatile memory cells, and each volatile memory cell includes a select transistor and a capacitor. The capacitor includes at least one contact electrically connected with the select transistor and having a second height corresponding to a first height of each cell string, and at least one second contact supplied with a ground voltage, having a third height corresponding to the first height of each cell string, adjacent to the at least one first contact, and electrically disconnected with the at least one first contact.

公开(公告)号：US20190189632A1

公开(公告)日：2019-06-20

申请号：US16030170

申请日：2018-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youn-Yeol LEE ,  Chanho Kim

IPC: H01L27/11575 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/04

Abstract: A memory device includes a substrate, a first memory structure including a plurality of first word lines stacked on the substrate in a direction perpendicular to a top surface of the substrate, an inter-metal layer on the first memory structure and including a plurality of intermediate pads connected with separate, respective first word lines of the plurality of first word lines, a second memory structure including a plurality of second word lines stacked on the inter-metal layer in the direction perpendicular to the top surface of the substrate, and an upper metal layer on the second memory structure and including a plurality of upper pads connected with separate, respective second word lines of the plurality of second word lines.

公开(公告)号：US11875855B2

公开(公告)日：2024-01-16

申请号：US17746393

申请日：2022-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwa Yun ,  Chanho Kim ,  Pansuk Kwak

IPC: G11C16/08 ,  G11C16/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A memory device including: a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of wordlines extended in a first direction and stacked in a second direction substantially perpendicular to the first direction; and a plurality of pass transistors disposed in the first semiconductor layer, wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of a plurality of signal lines and a first wordline of the plurality of wordlines, and wherein the plurality of signal lines are arranged at the same level as a common source line.

公开(公告)号：US11699693B2

公开(公告)日：2023-07-11

申请号：US17545522

申请日：2021-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jooyong Park ,  Chanho Kim ,  Daeseok Byeon

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L24/05 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes first and second chips. The first chip includes a memory cell array disposed on a first substrate, and first metal pads on a first uppermost metal layer of the first chip. The second chip includes peripheral circuits disposed on a second substrate, and second metal pads on a second uppermost metal layer of the second chip, the peripheral circuits operating the memory cell array. A first metal pad and a second metal pad are connected in a first area, the first metal pads being connected to the memory cell array and the second metal pad being connected to the peripheral circuits. A further first metal pad and a further second metal pad are connected in a second area, the further first metal pad being not connected to the memory cell array and the further second metal pad being connected to the peripheral circuits.

公开(公告)号：US20220352204A1

公开(公告)日：2022-11-03

申请号：US17860618

申请日：2022-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwa YUN ,  Chanho Kim ,  Dongku Kang

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11573

Abstract: A nonvolatile memory device includes a peripheral circuit including a first active region and a memory block including a second active region on the peripheral circuit. The memory block includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure, the second active region, and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer.