公开(公告)号：US11482596B2

公开(公告)日：2022-10-25

申请号：US17207690

申请日：2021-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum Kim ,  Seokhoon Kim ,  Kwanheum Lee ,  Choeun Lee ,  Sujin Jung

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/167 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes a channel, a first source/drain structure on a first side surface of the channel, a second source/drain structure on a second side surface of the channel, a gate structure surrounding the channel, an inner spacer layer on a side surface of the gate structure, and an outer spacer layer on an outer surface of the inner spacer layer. The first source/drain structure includes a first source/drain layer on the channel and a second source/drain layer on the first source/drain layer, and on a plane of the semiconductor device that passes through the channel, at least one of a first boundary line of the first source/drain layer in contact with the second source/drain layer and a second boundary line of the first source/drain layer in contact with the channel may be convex, extending toward the channel.

公开(公告)号：US11417776B2

公开(公告)日：2022-08-16

申请号：US16715431

申请日：2019-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sujin Jung ,  Junbeom Park ,  Kihwan Kim ,  Sunguk Jang ,  Youngdae Cho

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02

Abstract: A semiconductor device, including a silicon on insulator (SOI) substrate is disclosed. The device may include gate structures formed on the SOI substrate and being spaced apart from each other in a horizontal direction, and a plurality of channels spaced apart from each other in a vertical direction. Each of the channels may extend through each of the gate structures in the horizontal direction. The device may include a seed layer and a source/drain region. The source/drain region may be connected to the channels, and each sidewall of the source/drain region in the horizontal direction may have a concave-convex shape. The device may include a protruding portion of the source/drain region formed between the gate structures that protrudes in the horizontal direction compared to a non-protruding portion of the source/drain region formed between the channels.

公开(公告)号：US20220085202A1

公开(公告)日：2022-03-17

申请号：US17533499

申请日：2021-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngdae Cho ,  Sunguk Jang ,  Sujin Jung ,  Jungtaek Kim ,  Sihyung Lee

IPC: H01L29/78 ,  H01L29/423

Abstract: A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities. The second semiconductor layer may be formed on the first semiconductor layer, and may have a second concentration of impurities different from the first concentration of impurities. The semiconductor device may have good characteristics and high reliability.

公开(公告)号：US10797165B2

公开(公告)日：2020-10-06

申请号：US16116577

申请日：2018-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryeol Yoo ,  Jeongho Yoo ,  Sujin Jung ,  Youngdae Cho

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/02 ,  H01L27/092

Abstract: A semiconductor device includes a well region in a substrate, a semiconductor pattern on the well region, the semiconductor pattern including an impurity, and a gate electrode on the semiconductor pattern. A concentration of the impurity in the semiconductor pattern increases in a direction from an upper portion of the semiconductor pattern, adjacent to the gate electrode, to a lower portion of the semiconductor pattern, adjacent to the well region.

公开(公告)号：US09905676B2

公开(公告)日：2018-02-27

申请号：US15134556

申请日：2016-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum Kim ,  Kang Hun Moon ,  Choeun Lee ,  Sujin Jung ,  Yang Xu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/823425 ,  H01L21/823431 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a sidewall of the gate structure, anisotropically etching the substrate using the gate structure and the first etch mask as an etch mask to form a preliminary recess in the substrate, forming a sacrificial layer in the preliminary recess, forming a second etch mask on the first etch mask, etching the sacrificial layer and the substrate beneath the sacrificial layer using the gate structure and the first and second etch masks as an etch mask to form a source/drain recess in the substrate, and forming a source/drain in the source/drain recess. A sidewall of the source/drain recess may be recessed toward the gate structure relative to an outer surface of the second etch mask.

公开(公告)号：US20160322495A1

公开(公告)日：2016-11-03

申请号：US15138840

申请日：2016-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kanghun Moon ,  JinBum Kim ,  Kwan Heum Lee ,  Choeun Lee ,  Sujin Jung ,  Yang Xu

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/165 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes an active pattern protruding from a substrate and extending in a first direction, first and second gate electrodes intersecting the active pattern in a second direction intersecting the first direction, and a source/drain region disposed on the active pattern between the first and second gate electrodes. The source/drain region includes a first part adjacent to an uppermost surface of the active pattern and provided at a level lower than the uppermost surface of the active pattern, and a second part disposed under the first part so as to be in contact with the first part. A width of the first part along the first direction decreases in a direction away from the substrate, and a width of the second part along the first direction increases in a direction away from the substrate.

Abstract translation: 半导体器件包括从衬底突出并沿第一方向延伸的有源图案，在与第一方向相交的第二方向上与有源图案相交的第一和第二栅电极以及设置在第一和第二方向上的有源图案之间的源/漏区域 和第二栅电极。 源极/漏极区域包括与有源图案的最上表面相邻并且设置在比有源图案的最上表面低的水平面处的第一部分，以及设置在第一部分下方以与第一部分接触的第二部分 第一部分。 沿着第一方向的第一部分的宽度沿离开基板的方向减小，并且沿着第一方向的第二部分的宽度在远离基板的方向上增加。

公开(公告)号：US20250048696A1

公开(公告)日：2025-02-06

申请号：US18609885

申请日：2024-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KI HWAN KIM ,  Unki Kim ,  Chanyoung Kim ,  Jeongho Yoo ,  Ingyu Jang ,  Sujin Jung

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern sequentially stacked and vertically spaced apart, a source/drain pattern on the active pattern, and a gate electrode on the first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern, where the source/drain pattern includes a buffer layer and a main layer on the buffer layer, the main layer includes silicon that is doped with an impurity, an impurity concentration of the main layer is a first atomic fraction at a first level corresponding to the first semiconductor pattern, and the impurity concentration of the main layer is a second atomic fraction at a second level corresponding to the second semiconductor pattern.

公开(公告)号：US12154988B2

公开(公告)日：2024-11-26

申请号：US17585686

申请日：2022-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sujin Jung ,  Jinbum Kim ,  Dahye Kim ,  Ingyu Jang ,  Dongsuk Shin

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10

Abstract: Disclosed are a semiconductor device and a method of fabricating the same, the semiconductor device including an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern on the active pattern, connected to the source/drain pattern, and including stacked semiconductor patterns, a gate electrode extending in a first direction and crossing the channel pattern, and a gate insulating layer between the gate electrode and the channel pattern. The source/drain pattern includes first and second semiconductor layers, the first semiconductor layer including a center portion including a second outer side surface in contact with the gate insulating layer and an edge portion adjacent to a side of the center portion and including a first outer side surface in contact with the gate insulating layer. The second outer side surface is further recessed toward the second semiconductor layer, compared with the first outer side surface.

公开(公告)号：US11777032B2

公开(公告)日：2023-10-03

申请号：US17533499

申请日：2021-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngdae Cho ,  Sunguk Jang ,  Sujin Jung ,  Jungtaek Kim ,  Sihyung Lee

IPC: H01L29/78 ,  H01L29/423

CPC classification number: H01L29/785 ,  H01L29/42356 ,  H01L29/42392 ,  H01L2029/7858

Abstract: A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities. The second semiconductor layer may be formed on the first semiconductor layer, and may have a second concentration of impurities different from the first concentration of impurities. The semiconductor device may have good characteristics and high reliability.

公开(公告)号：US20220209013A1

公开(公告)日：2022-06-30

申请号：US17499979

申请日：2021-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kihwan Kim ,  Sunguk Jang ,  Sujin Jung ,  Youngdae Cho

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

Abstract: A semiconductor device includes an active region extending in a first direction; a plurality of channel layers on the active region; a gate structure extending in a second direction; and a source/drain region disposed on the active region, and connected to each of the plurality of channel layers, wherein the source/drain region includes a first epitaxial layer having a lower end portion and a sidewall portion extending continuously along lateral surfaces of the plurality of channel layers, the first epitaxial layer doped with a first impurity; and a second epitaxial layer on the first epitaxial layer, having a composition, different from a composition of the first epitaxial layer, and doped with a second impurity, wherein diffusivity of the first impurity in the composition of the first epitaxial layer is lower than the diffusivity that the second impurity would have in the composition of the first epitaxial layer.