公开(公告)号：US09070729B2

公开(公告)日：2015-06-30

申请号：US14497382

申请日：2014-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-wook Ji ,  Hyoung-yol Mun ,  Yeong-Iyeol Park ,  Tae-je Cho

IPC: H01L21/683 ,  H01L21/304 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/6835 ,  H01L21/02013 ,  H01L21/02016 ,  H01L21/304 ,  H01L21/6836 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2223/54493 ,  H01L2224/11 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wafer processing method, by which a device wafer may be aligned and bonded to a carrier wafer to perform a back grinding process for the device wafer and may be separated from the carrier wafer after performing the back grinding process, and a method of manufacturing a semiconductor device by using the wafer processing method are provided. The wafer processing method includes: disposing a first magnetic material on a front side of a wafer and disposing a second magnetic material on a carrier wafer, wherein a surface of the first magnetic material and a surface of the second magnetic material, which face each other, have opposite polarities; aligning and bonding the wafer to the carrier wafer by magnetic attraction between the first magnetic material and the second magnetic material; grinding a back side of the wafer to make the wafer thin; and separating the wafer from the carrier wafer.

Abstract translation: 一种晶片处理方法，通过该晶圆处理方法，可以将器件晶片对准并结合到载体晶片以对器件晶片进行背面磨削处理，并且可以在执行背面磨削工艺之后与载体晶片分离，并且制造 提供了使用晶片处理方法的半导体器件。 晶片处理方法包括：将第一磁性材料设置在晶片的前侧，并在载体晶片上设置第二磁性材料，其中第一磁性材料的表面和第二磁性材料的表面彼此面对 ，具有相反的极性; 通过第一磁性材料和第二磁性材料之间的磁吸引将晶片对准和结合到载体晶片; 研磨晶片的背面以使晶片变薄; 以及将晶片与载体晶片分离。

公开(公告)号：US08847378B2

公开(公告)日：2014-09-30

申请号：US13738322

申请日：2013-01-10

Applicant: Samsung Electronics Co., Ltd

Inventor： Yun-Seok Choi ,  Tae-je Cho

IPC: H01L23/02 ,  H01L23/48 ,  H01L25/10 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/11

Abstract: A semiconductor package includes a first semiconductor package, a second semiconductor package, and a package-connecting member. The first semiconductor package includes a first substrate, a chip stacking portion disposed on the first substrate and including a plurality of first semiconductor chips, and a first sealant for surrounding the chip stacking portion on the first substrate. The second semiconductor package includes a second substrate, at least one second semiconductor chip disposed on the second substrate, and a second sealant for surrounding the second semiconductor chip on the second substrate. The package-connecting member electrically connects the first semiconductor package and the second semiconductor package. The plurality of first semiconductor chips include a first chip including through silicon vias (TSVs) and a second chip electrically connected to the first chip via the TSVs, and the chip stacking portion includes an internal sealant for filling a space between the first chip and the second chip and extending to a side of the second chip.

Abstract translation: 半导体封装包括第一半导体封装，第二半导体封装和封装连接元件。 第一半导体封装包括第一衬底，设置在第一衬底上并包括多个第一半导体芯片的芯片堆叠部分，以及用于围绕第一衬底上的芯片堆叠部分的第一密封剂。 第二半导体封装包括第二衬底，设置在第二衬底上的至少一个第二半导体芯片和用于围绕第二衬底上的第二半导体芯片的第二密封剂。 封装连接部件电连接第一半导体封装和第二半导体封装。 多个第一半导体芯片包括通过硅通孔（TSV）的第一芯片和通过TSV与第一芯片电连接的第二芯片，并且芯片堆叠部分包括用于填充第一芯片和第二芯片之间的空间的内部密封剂 第二芯片并且延伸到第二芯片的一侧。