公开(公告)号：US09899337B2

公开(公告)日：2018-02-20

申请号：US15174411

申请日：2016-06-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gun-ho Chang ,  Tae-je Cho ,  Jong-bo Shim

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/27002 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2224/27 ,  H01L2924/00

Abstract: A semiconductor package includes a package member and a stress controlling layer. The package member includes an encapsulation layer and at least one chip. The encapsulation layer encapsulates the at least one chip. The stress controlling layer is disposed on a surface of the package member. The stress controlling layer has an internal stress to the extent that the stress controlling layer prevents the package member from having warpage.

公开(公告)号：US09515057B2

公开(公告)日：2016-12-06

申请号：US14541121

申请日：2014-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keum-hee Ma ,  Tae-je Cho ,  Ji-hwang Kim

IPC: H01L25/10 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/562 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor package includes: a package base substrate; at least one first semiconductor chip disposed on the package base substrate; a first molding member disposed at a same level as the at least one first semiconductor chip and that does not cover an upper surface of the at least one first semiconductor chip; at least one second semiconductor chip stacked on the at least one first semiconductor chip so as to extend over the at least one first semiconductor chip and the first molding member, wherein the at least one first semiconductor chip and at least part of the first molding member are disposed between the package base substrate and the at least one second semiconductor chip; and a second molding member disposed at a same level as the at least one second semiconductor chip.

Abstract translation: 半导体封装包括：封装基底; 设置在所述封装基板上的至少一个第一半导体芯片; 第一模制构件，其设置在与所述至少一个第一半导体芯片相同的水平面处，并且不覆盖所述至少一个第一半导体芯片的上表面; 至少一个第二半导体芯片，堆叠在所述至少一个第一半导体芯片上，以便在所述至少一个第一半导体芯片和所述第一模制构件上延伸，其中所述至少一个第一半导体芯片和所述第一模制构件的至少一部分 设置在所述封装基底基板和所述至少一个第二半导体芯片之间; 以及设置在与所述至少一个第二半导体芯片相同水平面的第二模制构件。

公开(公告)号：US20160013091A1

公开(公告)日：2016-01-14

申请号：US14723642

申请日：2015-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-hwang Kim ,  Un-byoung Kang ,  Cha-jea Jo ,  Tae-je Cho

IPC: H01L21/768 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L21/486 ,  H01L21/563 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A method of manufacturing a semiconductor package includes forming a bonding layer on a carrier substrate, bonding an inner substrate to the carrier substrate, removing the carrier substrate, and forming a gap-filling portion by removing a portion of the bonding layer to expose a portion of a solder ball provided in the inner substrate. The inner substrate may be mounted on a package substrate and a semiconductor chip may be mounted on the inner substrate.

Abstract translation: 一种半导体封装的制造方法，其特征在于，在载体基板上形成接合层，将内部基板与载体基板接合，除去载体基板，通过除去接合层的一部分而形成间隙填充部， 设置在内部基板中的焊球。 内部基板可以安装在封装基板上，半导体芯片可以安装在内部基板上。

公开(公告)号：US20130221493A1

公开(公告)日：2013-08-29

申请号：US13765696

申请日：2013-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-yeon Kim ,  Tae-hong Min ,  Yeong-kwon Ko ,  Tae-je Cho

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/3135 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/15311

Abstract: Semiconductor packages are disclosed. A semiconductor package includes: a first chip that includes a chip region and scribe regions at edges of the chip region, wherein the chip region comprises integrated circuit units and main through substrate vias electrically connected to the integrated circuit units; and a second chip that is bonded onto the first chip. The semiconductor package includes dummy conductive connectors including at least dummy wiring lines, the dummy conductive connectors electrically connected to the main through substrate vias at one end, and not capable of forming an electrical connection at the other end.

Abstract translation: 公开了半导体封装。 半导体封装包括：第一芯片，其在芯片区域的边缘处包括芯片区域和划线区域，其中芯片区域包括电连接到集成电路单元的集成电路单元和主通孔衬底通孔; 以及接合到第一芯片上的第二芯片。 半导体封装包括至少包括虚拟布线的虚拟导电连接器，虚拟导电连接器在一端电连接到主通孔衬底通孔，而不能在另一端形成电连接。

公开(公告)号：US20170117264A1

公开(公告)日：2017-04-27

申请号：US15285500

申请日：2016-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-young Lee ,  Hyun-soo Chung ,  Tae-je Cho

IPC: H01L25/00 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/18162

Abstract: A method may include providing a first semiconductor chip and a first insulating layer surrounding lateral sides of the first semiconductor chip; providing a second semiconductor chip and a second insulating layer surrounding lateral sides of the second semiconductor chip; providing a third insulating layer below the first semiconductor chip and first insulating layer, so that the first semiconductor chip is between the third insulating layer and the second semiconductor chip, the third insulating layer forming a package substrate; providing a plurality of external connection terminals on the third insulating layer, such that the third insulating layer has a first surface facing the first semiconductor chip and a second surface facing the external connection terminals; providing a first redistribution line on the first surface of the third insulating layer and extending horizontally along the first surface of the third insulating layer, the first redistribution line contacting a first conductive pad of the first semiconductor chip; and providing a second redistribution line connected to a second conductive pad at a surface of the second semiconductor chip, the second redistribution line passing through the first insulating layer to contact the first redistribution line.

公开(公告)号：US20170084561A1

公开(公告)日：2017-03-23

申请号：US15262040

申请日：2016-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Seung-kwan Ryu ,  Ju-il Choi ,  Tae-je Cho ,  Yong-hwan Kwon

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02205 ,  H01L2224/02215 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/10145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/1162 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/13076 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/1312 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13564 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/07025 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012

Abstract: An electronic device is provided, which includes a substrate having an electrically conductive contact pad thereon and an electrically conductive connection terminal on the contact pad. The connection terminal includes an electrically conductive pillar structure and a solder layer that extends on the pillar structure and contacts a protruding portion of a sidewall of the pillar structure. The pillar structure can include a lower pillar layer, a diffusion barrier layer on the lower pillar layer and an upper pillar layer on the diffusion barrier layer. In some additional embodiments of the invention, the protruding portion of the sidewall of the pillar structure includes an outermost portion of an upper surface of the diffusion barrier layer. This can be achieved by making a width of the diffusion barrier layer greater than a width of the upper pillar layer when viewed in transverse cross-section.

公开(公告)号：US09589945B2

公开(公告)日：2017-03-07

申请号：US14804880

申请日：2015-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cha-jea Jo ,  Yun-hyeok Im ,  Tae-je Cho

IPC: H01L25/18 ,  H01L23/367 ,  H01L23/48 ,  H01L25/065 ,  H01L23/36 ,  H01L23/427 ,  H01L23/532 ,  H01L23/31

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/427 ,  H01L23/481 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/16195

Abstract: A semiconductor package includes a package base substrate, at least one first semiconductor chip disposed on the package base substrate, and at least one stacked semiconductor chip structure disposed on the package base substrate adjacent to the at least one first semiconductor chip. The at least one stacked semiconductor chip includes a plurality of second semiconductor chips. A penetrating electrode region including a plurality of penetrating electrodes is disposed adjacent to an edge of the at least one stacked semiconductor chip structure.

Abstract translation: 半导体封装包括封装基底基板，设置在封装基底基板上的至少一个第一半导体芯片以及设置在与该至少一个第一半导体芯片相邻的封装基底基板上的至少一个层叠半导体芯片结构。 所述至少一个层叠半导体芯片包括多个第二半导体芯片。 包括多个穿透电极的穿透电极区域设置成与所述至少一个堆叠的半导体芯片结构的边缘相邻。

公开(公告)号：US20170047294A1

公开(公告)日：2017-02-16

申请号：US15174411

申请日：2016-06-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： GUN-HO CHANG ,  Tae-je Cho ,  Jong-bo Shim

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/27002 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2224/27 ,  H01L2924/00

Abstract: A semiconductor package includes a package member and a stress controlling layer. The package member includes an encapsulation layer and at least one chip. The encapsulation layer encapsulates the at least one chip. The stress controlling layer is disposed on a surface of the package member. The stress controlling layer has an internal stress to the extent that the stress controlling layer prevents the package member from having warpage.

Abstract translation: 半导体封装包括封装构件和应力控制层。 封装构件包括封装层和至少一个芯片。 封装层封装至少一个芯片。 应力控制层设置在包装件的表面上。 应力控制层具有内应力至应力控制层防止包装件翘曲的程度。

公开(公告)号：US20150221517A1

公开(公告)日：2015-08-06

申请号：US14613822

申请日：2015-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-mi Kim ,  Un-byoung Kang ,  Tae-je Cho ,  Jung-seok Ahn

IPC: H01L21/306 ,  H01L21/768 ,  H01L21/304 ,  H01L21/78

CPC classification number: H01L21/304 ,  C09J7/22 ,  C09J7/30 ,  C09J2201/36 ,  C09J2203/326 ,  C09J2433/00 ,  C09J2463/00 ,  H01L21/30604 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L24/03 ,  H01L24/06 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16238 ,  H01L2224/16245 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device capable of thinning a semiconductor chip can be performed while preventing the semiconductor chip from being damaged. A method of manufacturing a semiconductor device includes: preparing a semiconductor substrate including a plurality of semiconductor chips, attaching the semiconductor substrate to a support substrate with an adhesive support film, removing an edge region of the semiconductor substrate together with a portion of the adhesive support film between the edge region of the semiconductor substrate and the support substrate and, thereafter, polishing the semiconductor substrate to thin the semiconductor substrate.

Abstract translation: 可以在防止半导体芯片损坏的同时进行制造能够使半导体芯片变薄的半导体器件的制造方法。 一种制造半导体器件的方法包括：制备包括多个半导体芯片的半导体衬底，用粘合剂支撑膜将半导体衬底附着到支撑衬底上，与粘合剂支撑体的一部分一起去除半导体衬底的边缘区域 在半导体衬底的边缘区域和支撑衬底之间形成薄膜，然后对半导体衬底进行抛光以使半导体衬底变薄。

公开(公告)号：US20150093880A1

公开(公告)日：2015-04-02

申请号：US14497382

申请日：2014-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-wook Ji ,  Hyoung-yol Mun ,  Yeong-Iyeol Park ,  Tae-je Cho

IPC: H01L21/683 ,  H01L21/768 ,  H01L21/304

CPC classification number: H01L21/6835 ,  H01L21/02013 ,  H01L21/02016 ,  H01L21/304 ,  H01L21/6836 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2223/54493 ,  H01L2224/11 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wafer processing method, by which a device wafer may be aligned and bonded to a carrier wafer to perform a back grinding process for the device wafer and may be separated from the carrier wafer after performing the back grinding process, and a method of manufacturing a semiconductor device by using the wafer processing method are provided. The wafer processing method includes: disposing a first magnetic material on a front side of a wafer and disposing a second magnetic material on a carrier wafer, wherein a surface of the first magnetic material and a surface of the second magnetic material, which face each other, have opposite polarities; aligning and bonding the wafer to the carrier wafer by magnetic attraction between the first magnetic material and the second magnetic material; grinding a back side of the wafer to make the wafer thin; and separating the wafer from the carrier wafer.

Abstract translation: 一种晶片处理方法，通过该晶圆处理方法，可以将器件晶片对准并结合到载体晶片以对器件晶片进行背面磨削处理，并且可以在执行背面磨削工艺之后与载体晶片分离，并且制造 提供了使用晶片处理方法的半导体器件。 晶片处理方法包括：将第一磁性材料设置在晶片的前侧，并将第二磁性材料设置在载体晶片上，其中第一磁性材料的表面和第二磁性材料的表面彼此面对 ，具有相反的极性; 通过第一磁性材料和第二磁性材料之间的磁吸引将晶片对准和结合到载体晶片; 研磨晶片的背面以使晶片变薄; 以及将晶片与载体晶片分离。