公开(公告)号：US11024393B1

公开(公告)日：2021-06-01

申请号：US16738677

申请日：2020-01-09

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Huai-Yuan Tseng ,  Ken Oowada ,  Deepanshu Dutta

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24

Abstract: An apparatus comprises a driver circuit, sense circuit, and die controller. The driver circuit supplies a pass voltage to a selected word line and unselected word lines, a sense voltage to an adjacent word line, and a bit line voltage to bit lines coupled to selected and unselected word lines. The sense circuit determines nonconducting and conducting memory cells on the adjacent word line. The die controller then directs the driver circuit to ramp the sense voltage on the adjacent word line to the pass voltage and ramp the pass voltage on the selected word line to ground. The die controller then directs the driver circuit to ramp the bit line voltage for bit lines coupled to nonconducting memory cells to a bit line compensation voltage and directs the sense circuit to read memory cells of the selected word line based on the bit line compensation voltage.

公开(公告)号：US20210142841A1

公开(公告)日：2021-05-13

申请号：US16683209

申请日：2019-11-13

Applicant: SanDisk Technologies LLC

Inventor： Masatoshi Nishikawa ,  Hardwell Chibvongodze ,  Ken Oowada

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/56 ,  H01L27/06

Abstract: A three-dimensional (3D) memory is provided, including a memory array chip and a complementary metal-oxide semiconductor (CMOS) chip disposed on the memory array chip. The memory chip provides double write/read throughput and includes a lower region with a lower array of memory cells, lower word lines, and a lower bit line, while an upper region includes an upper array of memory cells, upper word lines, and an upper bit line. A source line is disposed between the lower and upper regions and is connected to both the lower array of memory cells and the upper array of memory cells.

公开(公告)号：US11004518B2

公开(公告)日：2021-05-11

申请号：US16456045

申请日：2019-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko Sakakibara ,  Hiroki Yabe ,  Ken Oowada ,  Masaaki Higashitani

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/1157 ,  G11C16/34 ,  G11C11/56 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519

Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.

公开(公告)号：US20200335518A1

公开(公告)日：2020-10-22

申请号：US16919744

申请日：2020-07-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Masatoshi Nishikawa ,  Ken Oowada

IPC: H01L27/11582 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L23/528 ,  H01L21/311 ,  H01L21/762 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556 ,  H01L21/28

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The alternating stack includes a first region in which all layers of the alternating stack are present and a second region in which at least a topmost one of the electrically conductive layers is absent. First memory opening fill structures extend through the first region of the alternating stack, and second memory opening fill structures extend through the second region of the alternating stack. The first memory opening fill structures have a greater height than the second memory opening fill structures. Pocket doping regions extending over a respective subset of topmost electrically conductive layers for the memory opening fill structures can be formed to provide higher threshold voltages and to enable selective activation of vertical semiconductor channels connected a same bit line.

公开(公告)号：US20230197172A1

公开(公告)日：2023-06-22

申请号：US17557492

申请日：2021-12-21

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Ken Oowada ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/3454 ,  G11C16/3409 ,  G11C16/102 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08

Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to one of a plurality of word lines including an edge word line and a plurality of other data word lines. The memory cells are disposed in memory holes organized in rows grouped in a plurality of strings. The rows include full circle rows and semi-circle rows. A control means is configured to program the memory cells connected to the edge word line and in the semi-circle rows of a first one and a second one of the plurality of strings to a predetermined one of a plurality of data states in a first program operation. The control means then selects both the first one and the second one of the plurality of strings together and programs the memory cells of the full circle rows together in a second program operation.

公开(公告)号：US20230128177A1

公开(公告)日：2023-04-27

申请号：US17507119

申请日：2021-10-21

Applicant: SanDisk Technologies LLC

Inventor： Ken Oowada ,  Natsu Honda

IPC: G11C16/04 ,  G11C16/14

Abstract: Technology is disclosed for applying a positive temperature coefficient (Tco) voltage to a control terminal of a dummy select transistor. The dummy select transistor resides on a NAND string having non-volatile memory cells and a regular select transistor. The dummy select transistor is typically ON (or conductive) during memory operations such as selected string program, read, and verify. In an aspect, the positive Tco voltage is applied to the control terminal of a dummy select transistor during a program operation. Applying the positive Tco voltage during program operations reduces or eliminates program disturb to the dummy select transistor. In some aspects, the dummy select transistor is used to generate a gate induced drain leakage (GIDL) current during an erase operation. In some aspects, the dummy select transistor is a depletion mode transistor.

公开(公告)号：US20230050955A1

公开(公告)日：2023-02-16

申请号：US17399498

申请日：2021-08-11

Applicant: SanDisk Technologies LLC

Inventor： Dengtao Zhao ,  Gerrit Jan Hemink ,  Xiang Yang ,  Ken Oowada ,  Guirong Liang

IPC: G11C16/34 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24

Abstract: To help reduce program disturbs in non-selected NAND strings of a non-volatile memory, a sub-block based boosting scheme in introduced. For a three dimensional NAND memory structure, in which the memory cells above a joint region form an upper sub-block and memory cells below the joint region form a lower sub-block, dummy word lines in the joint region act as select gates to allow boosting at the sub-block level when the lower block is being programmed in a reverse order.

公开(公告)号：US11545221B2

公开(公告)日：2023-01-03

申请号：US17360572

申请日：2021-06-28

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Gerrit Jan Hemink ,  Ken Oowada ,  Toru Miwa

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C8/18 ,  G11C8/12

Abstract: Technology is disclosed herein for concurrently programming the same data pattern in multiple sets of non-volatile memory cells. Voltage are applied to bit lines in accordance with a data pattern. A select voltage is applied to drain select gates of multiple sets of NAND strings. The system concurrently applies a program pulse to control gates of a different set of selected memory cells in each respective set of the multiple sets of the NAND strings while the select voltage is applied to the drain select gates of the multiple sets of the NAND strings and the voltages are applied to the plurality of bit lines to concurrently program the data pattern into each set of the selected memory cells.

公开(公告)号：US20220404989A1

公开(公告)日：2022-12-22

申请号：US17349306

申请日：2021-06-16

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Toru Miwa ,  Ken Oowada ,  Gerrit Jan Hemink

IPC: G06F3/06

Abstract: Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. One or more initial pages of data are programmed into both a primary block and a first backup block in a first program pass. A power loss then occurs which can corrupt the data or otherwise prevent reading of the one or more initial pages of data from the primary block. The one or more initial pages of data are read from the first backup block and used to perform a second program pass in which one or more additional pages of data are programmed into the primary block. Single bit per cell data can be stored in a second backup block to decode the one or more initial pages of data as read from the first backup block.

公开(公告)号：US11501821B2

公开(公告)日：2022-11-15

申请号：US17090080

申请日：2020-11-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki Ogawa ,  Ken Oowada ,  Mitsuteru Mushiga

IPC: G11C16/06 ,  G11C11/408 ,  G11C5/06 ,  G11C5/02 ,  G11C11/4094

Abstract: A semiconductor structure includes a peripheral circuit, a first three-dimensional memory array overlying the peripheral circuit and including a first alternating stack of first insulating layers and first electrically conductive layers containing first word lines and first select lines, and first memory stack structures vertically extending through the first alternating stack, and a second three-dimensional memory array overlying the first three-dimensional memory array and including a second alternating stack of second insulating layers and second electrically conductive layers containing second word lines and second select lines, and second memory stack structures vertically extending through the second alternating stack. The peripheral circuit includes a first word line driver circuit having first word line driver output nodes electrically connected to at least some of the first word lines and at least some of the second word lines, and each first word line is electrically connected to a respective second word line.