公开(公告)号：US20150294938A1

公开(公告)日：2015-10-15

申请号：US14669527

申请日：2015-03-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Chieh-Yuan Chi ,  Mu-Hsuan Chan

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/31 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76879 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/53228 ,  H01L23/5389 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a conductive via structure is provided, which includes the steps of: forming in an encapsulant a plurality of openings penetrating therethrough; forming a dielectric layer on the encapsulant and in the openings of the encapsulant; forming a plurality of vias in the dielectric layer in the openings of the encapsulant; and forming a conductive material in the vias to thereby form conductive vias. Therefore, by filling the openings having rough wall surfaces with the dielectric layer so as to form the vias having even wall surfaces, the present invention improves the quality of the conductive vias.

Abstract translation: 提供了一种用于制造导电通孔结构的方法，其包括以下步骤：在密封剂中形成贯穿其中的多个开口; 在密封剂和密封剂的开口中形成介电层; 在密封剂的开口中的电介质层中形成多个通孔; 以及在通路中形成导电材料，从而形成导电通路。 因此，通过用具有电介质层的具有粗糙壁面的开口填充以形成具有均匀的壁表面的通孔，本发明提高了导电通孔的质量。

公开(公告)号：US20150255311A1

公开(公告)日：2015-09-10

申请号：US14716272

申请日：2015-05-19

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Wan-Ting Chen ,  Mu-Hsuan Chan ,  Yi-Chian Liao ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L21/56 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/561 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/28 ,  H01L23/31 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element.

Abstract translation: 提供半导体封装，包括：载体; 至少设置在所述载体上的插入件; 形成在所述载体上的密封剂，用于在暴露所述插入件的顶侧的同时封装所述插入件; 设置在所述插入件的顶侧的半导体元件; 以及形成在插入件和半导体元件之间的粘合剂。 通过用封装剂封装插入件，避免了插入器的翘曲，并且为了将半导体元件设置在其上提供平坦的表面，从而提高了插入件与半导体元件之间的电连接的可靠性。

公开(公告)号：US08952537B2

公开(公告)日：2015-02-10

申请号：US13677904

申请日：2012-11-15

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Feng Chan ,  Mu-Hsuan Chan ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L23/488 ,  H01L21/441 ,  H01L23/48

CPC classification number: H01L24/81 ,  H01L21/441 ,  H01L21/56 ,  H01L23/145 ,  H01L23/147 ,  H01L23/488 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.

Abstract translation: 用于形成在具有多个接合焊盘的基板上的导电凸块结构。 导电凸块结构包括在接合焊盘上形成的第一金属层，形成在第一金属层上的第二金属层和形成在第二金属层上的第三金属层。 第二金属层的第二熔点高于第三金属层的第三熔点。 因此，首先对第三金属层进行热压接，从而将基板粘合到另一基板上，然后进行回流处理，使第二金属层和第三金属层彼此熔融 从而形成合金部分，从而避免基板的开裂。

公开(公告)号：US20140342505A1

公开(公告)日：2014-11-20

申请号：US14151153

申请日：2014-01-09

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Mu-Hsuan Chan ,  Chieh-Yuan Chi ,  Yan-Yi Liao

IPC: H01L21/52 ,  H01L21/78

CPC classification number: H01L21/52 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a carrier; disposing at least a semiconductor element on the carrier; forming an encapsulant on the carrier and the semiconductor element for encapsulating the semiconductor element; removing the carrier; disposing a pressure member on the encapsulant; and forming an RDL structure on the semiconductor element and the encapsulant, thereby suppressing internal stresses through the pressure member so as to mitigate warpage on edges of the encapsulant.

Abstract translation: 公开了一种半导体封装的制造方法，其包括以下步骤：提供载体; 在载体上设置至少一个半导体元件; 在所述载体和所述半导体元件上形成用于封装所述半导体元件的密封剂; 移除载体; 将压力构件设置在密封剂上; 以及在半导体元件和密封剂上形成RDL结构，由此抑制通过压力构件的内部应力，从而减轻密封剂边缘的翘曲。

公开(公告)号：US20140008787A1

公开(公告)日：2014-01-09

申请号：US13677904

申请日：2012-11-15

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chien-Feng Chan ,  Mu-Hsuan Chan ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L23/488 ,  H01L21/441

CPC classification number: H01L24/81 ,  H01L21/441 ,  H01L21/56 ,  H01L23/145 ,  H01L23/147 ,  H01L23/488 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.

Abstract translation: 用于形成在具有多个接合焊盘的基板上的导电凸块结构。 导电凸块结构包括在接合焊盘上形成的第一金属层，形成在第一金属层上的第二金属层和形成在第二金属层上的第三金属层。 第二金属层的第二熔点高于第三金属层的第三熔点。 因此，首先对第三金属层进行热压接，从而将基板粘合到另一基板上，然后进行回流处理，使第二金属层和第三金属层彼此熔融 从而形成合金部分，从而避免基板的开裂。