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    PHASE-CHANGE MEMORY DEVICE HAVING PHASE-CHANGE REGION DIVIDED INTO MULTI LAYERS AND OPERATING METHOD THEREOF
    22.
    发明申请
    PHASE-CHANGE MEMORY DEVICE HAVING PHASE-CHANGE REGION DIVIDED INTO MULTI LAYERS AND OPERATING METHOD THEREOF 审中-公开
    具有相变区域的相变存储器件分为多层及其操作方法

    公开(公告)号：US20140301137A1

    公开(公告)日：2014-10-09

    申请号：US14309430

    申请日：2014-06-19

    Applicant: SK hynix Inc.

    Inventor： Jin Hyock KIM ,  Su Jin CHAE ,  Young Seok KWON ,  Hae Chan PARK

    IPC: H01L45/00 ,  G11C13/00

    CPC classification number: G11C13/0004 ,  G11C11/5678 ,  G11C13/0069 ,  G11C2013/0092 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

    Abstract: A phase-change memory device including a multi-level cell and an operation method thereof are provided. The device includes a first phase-change material layer to which a current is provided from a heating electrode, and a second phase-change material layer formed with continuity to the first phase-change material layer and having a different width from the first phase-change material layer, and to which a current is provided from the heating electrode. The second phase-change material layer includes a material having smaller resistivity and a lower crystallization rate than the first phase-change material layer.

    Abstract translation: 提供一种包括多电平单元的相变存储器件及其操作方法。 该装置包括从加热电极提供电流的第一相变材料层和与第一相变材料层连续形成且与第一相变材料层的宽度不同的第二相变材料层， 改变材料层，并且从加热电极提供电流。 第二相变材料层包括具有比第一相变材料层更低的电阻率和更低的结晶速率的材料。

    HIGH VOLTAGE GENERATING CIRCUIT FOR RESISTIVE MEMORY APPARATUS
    24.
    发明申请
    HIGH VOLTAGE GENERATING CIRCUIT FOR RESISTIVE MEMORY APPARATUS 有权
    用于电阻记忆装置的高压发生电路

    公开(公告)号：US20140169065A1

    公开(公告)日：2014-06-19

    申请号：US13846327

    申请日：2013-03-18

    Applicant: SK HYNIX INC.

    Inventor： Hae Chan PARK

    IPC: G11C13/00

    CPC classification number: G11C13/0038 ,  G11C13/0004

    Abstract: A high voltage generating circuit for a resistive memory apparatus is provided. The high voltage generating circuit includes a capacitor spaced from a semiconductor substrate and electrically insulated from the semiconductor substrate. A switching device, which is electrically connected to the capacitor, is electrically insulated from the semiconductor substrate.

    Abstract translation: 提供了一种用于电阻式存储装置的高电压产生电路。 高电压发生电路包括与半导体衬底间隔开并与半导体衬底电绝缘的电容器。 电连接到电容器的开关器件与半导体衬底电绝缘。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    25.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220020686A1

    公开(公告)日：2022-01-20

    申请号：US17491775

    申请日：2021-10-01

    Applicant: SK hynix Inc.

    Inventor： Hae Chan PARK ,  Jang Won KIM ,  Jae Taek KIM

    IPC: H01L23/522 ,  H01L45/00 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/24

    Abstract: The present technology relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another, a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack, a plurality of channel plugs vertically formed through the first stack and the second stack, and at least one dummy plug vertically formed through the second without passing through the first stack.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    26.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20210028105A1

    公开(公告)日：2021-01-28

    申请号：US16696013

    申请日：2019-11-26

    Applicant: SK hynix Inc.

    Inventor： Hae Chan PARK ,  Jang Won KIM ,  Jae Taek KIM

    IPC: H01L23/522 ,  H01L45/00 ,  H01L27/24 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/528

    Abstract: The present technology relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another, a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack, a plurality of channel plugs vertically formed through the first stack and the second stack, and at least one dummy plug vertically formed through the second without passing through the first stack.

    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    27.
    发明申请
    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190312057A1

    公开(公告)日：2019-10-10

    申请号：US16448844

    申请日：2019-06-21

    Applicant: SK hynix Inc.

    Inventor： Hae Chan PARK ,  Jang Won KIM ,  Gong Hyun SA

    IPC: H01L27/11582 ,  H01L21/02 ,  H01L21/762

    Abstract: A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.

    DATA PROCESSING SYSTEM HAVING COMBINED MEMORY BLOCK AND STACK PACKAGE
    28.
    发明申请
    DATA PROCESSING SYSTEM HAVING COMBINED MEMORY BLOCK AND STACK PACKAGE 审中-公开
    具有组合记忆块和堆叠包的数据处理系统

    公开(公告)号：US20160210235A1

    公开(公告)日：2016-07-21

    申请号：US15063012

    申请日：2016-03-07

    Applicant: SK hynix Inc.

    Inventor： Hae Chan PARK ,  Sung Cheoul KIM ,  Tae Ho KIM

    IPC: G06F12/08 ,  G06F13/40

    CPC classification number: G06F13/4022 ,  G06F2212/451 ,  G11C11/005 ,  G11C11/5607 ,  G11C11/5678 ,  G11C13/0004 ,  G11C16/06 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2213/71 ,  G11C2213/79 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A data processing system includes a central processing unit (CPU), a control block configured to interface with the CPU, a cache memory configured to interface with the control block and arranged to be spaced from the CPU by a first distance, and a combined memory block configured to interface with the control block, arranged to be spaced from the CPU by a second distance larger than the first distance, and configured of a working memory and a storage memory. The combined memory block is configured of a plurality of stacked memory layers, each configured of a plurality of variable resistance memory cells. The working memory is allocated to one memory layer selected among the plurality of memory layers. The storage memory is allocated to remaining memory layers among the plurality of memory layers.

    Abstract translation: 数据处理系统包括中央处理单元（CPU），配置成与CPU接口的控制块，配置为与控制块接口并被布置为与CPU间隔第一距离的高速缓存存储器，以及组合存储器 其被配置为与所述控制块接口，被布置成与所述CPU间隔大于所述第一距离的第二距离，并且由工作存储器和存储存储器构成。 组合存储块由多个堆叠存储器层构成，每个堆叠存储层由多个可变电阻存储单元构成。 工作存储器被分配给在多个存储器层中选择的一个存储器层。 存储存储器被分配给多个存储器层中的剩余存储器层。

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