公开(公告)号：US20220300205A1

公开(公告)日：2022-09-22

申请号：US17461451

申请日：2021-08-30

Applicant: SK hynix Inc.

Inventor： Se Ho LEE

IPC: G06F3/06

Abstract: Disclosed are a controller that controls a memory device, and an operating method of the controller. The controller may include a host interface suitable for fetching a write command received from a host; and a processor suitable for controlling a write operation of the memory device in response to the fetched write command, wherein, when a workload of a background operation of the processor is greater than a workload of a host write operation, the host interface is further suitable for: determining a delay amount of time and providing the host with a completion response to the write command after delaying the completion response by the delay amount of time.

公开(公告)号：US20210202835A1

公开(公告)日：2021-07-01

申请号：US16904825

申请日：2020-06-18

Applicant: SK hynix Inc.

Inventor： Jae Hyun HAN ,  Hyangkeun YOO ,  Se Ho LEE

IPC: H01L45/00

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a resistance change layer disposed over the substrate, a gate insulation layer disposed on the resistance change layer, a gate electrode layer disposed on the gate insulation layer, and a first electrode pattern layer and a second electrode pattern layer that are disposed respectively over the substrate and disposed to contact a different portion of the resistance change layer.

公开(公告)号：US20210074763A1

公开(公告)日：2021-03-11

申请号：US16844806

申请日：2020-04-09

Applicant: SK hynix Inc.

Inventor： Jae Hyun HAN ,  Hyangkeun YOO ,  Se Ho LEE

IPC: H01L27/24 ,  H01L45/00 ,  H01L29/24

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a gate electrode structure disposed on the substrate, a gate dielectric layer covering at least a portion of a sidewall surface of the gate electrode structure on the substrate, a channel layer and a resistance change structure that are sequentially disposed on the gate dielectric layer, and a plurality of bit line structures disposed inside the resistance change structure.

公开(公告)号：US20200212206A1

公开(公告)日：2020-07-02

申请号：US16701931

申请日：2019-12-03

Applicant: SK hynix Inc.

Inventor： Bo Yun KIM ,  Se Ho LEE

IPC: H01L29/66 ,  H01L29/792 ,  H01L21/02 ,  H01L27/11582

Abstract: In a method of fabricating a nonvolatile memory device according an embodiment, a first tunnel oxide layer, a nitrogen supply layer, and a second tunnel oxide layer having a density lower than that of the first tunnel oxide layer are formed on a substrate. Nitrogen in the nitrogen supply layer is diffused into the second tunnel oxide layer to convert at least a portion of the second tunnel oxide layer into an oxynitride layer.

公开(公告)号：US20200212060A1

公开(公告)日：2020-07-02

申请号：US16558678

申请日：2019-09-03

Applicant: SK hynix Inc.

Inventor： Hyangkeun YOO ,  Ju Ry SONG ,  Se Ho LEE ,  Jae Gil LEE

IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/267 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a cell electrode structure disposed on the substrate and including interlayer insulating layers and gate electrode layers that are alternately stacked, a trench penetrating the cell structure on the substrate, a charge storage structure disposed on a sidewall surface of the trench, and a channel structure disposed adjacent to the charge storage structure and extending in a direction parallel to the sidewall surface. The channel structure includes a separate hole conduction layer and an adjacent and separate electron conduction layer. A control channel layer disposed on a control dielectric layer is a portion of the electron conduction layer configured to electrically connect to the channel structure, and to the charge storage structure. A control dielectric layer and a charge barrier layer are discrete but contiguous from the control channel structure to the charge storage structure.

公开(公告)号：US20150009752A1

公开(公告)日：2015-01-08

申请号：US14494355

申请日：2014-09-23

Applicant: SK hynix Inc.

Inventor： Hae Chan PARK ,  Se Ho LEE

IPC: G11C13/00

CPC classification number: G11C13/0004 ,  G11C11/21 ,  G11C11/5678 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/0078 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  H01L45/04

Abstract: A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level.

公开(公告)号：US20140204664A1

公开(公告)日：2014-07-24

申请号：US14219549

申请日：2014-03-19

Applicant: SK HYNIX INC.

Inventor： Se Ho LEE

IPC: G11C13/00

CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097

Abstract: A method of driving phase change memory device includes initializing all memory cells and programming individually at least two selected memory cells disposed at random positions, wherein the selected memory cells are selected among the initialized memory cells.

Abstract translation: 一种驱动相变存储器件的方法包括：初始化所有存储器单元，并且单独编程设置在随机位置的至少两个选定的存储单元，其中所选择的存储器单元在初始化的存储器单元中被选择。

公开(公告)号：US20140054537A1

公开(公告)日：2014-02-27

申请号：US13791468

申请日：2013-03-08

Applicant: SK HYNIX INC.

Inventor： Seung Yun LEE ,  Hae Chan PARK ,  Myoung Sub KIM ,  Sung Bin HONG ,  Se Ho LEE ,  Jung Won SEO

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/16 ,  H01L45/1683

Abstract: A resistive memory device capable of preventing disturbance is provided. The resistive memory device includes a lower electrode formed on a semiconductor substrate, a variable resistor disposed on the lower electrode, an upper electrode disposed on the variable resistor, and an interlayer insulating layer configured to insulate the variable resistor. The interlayer insulating layer may include an air-gap area in at least a portion thereof.

Abstract translation: 提供能够防止干扰的电阻式存储装置。 电阻式存储器件包括形成在半导体衬底上的下电极，设置在下电极上的可变电阻器，设置在可变电阻器上的上电极以及被配置为使可变电阻器绝缘的层间绝缘层。 层间绝缘层的至少一部分中可以包括气隙区域。

公开(公告)号：US20220123021A1

公开(公告)日：2022-04-21

申请号：US17560248

申请日：2021-12-22

Applicant: SK hynix Inc.

Inventor： Hyangkeun YOO ,  Jae Gil LEE ,  Se Ho LEE

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L29/51 ,  H01L21/28

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an electrode stack disposed on the substrate, the electrode stack including an interlayer insulation layer and a gate electrode structure that are alternately stacked in a direction perpendicular to the substrate, a trench penetrating the electrode stack to expose sidewall surfaces of the interlayer insulation layer and the gate electrode structure, a gate dielectric layer disposed along a sidewall surface of the trench, the gate dielectric layer including a ferroelectric portion and a non-ferroelectric portion, and a channel layer disposed to adjacent to the gate dielectric layer. The ferroelectric portion is in contact with the gate electrode structure, and the non-ferroelectric portion is in contact with the interlayer insulation layer.

公开(公告)号：US20220013540A1

公开(公告)日：2022-01-13

申请号：US17484481

申请日：2021-09-24

Applicant: SK hynix Inc.

Inventor： Hyangkeun YOO ,  Ju Ry SONG ,  Se Ho LEE ,  Jae Gil LEE

IPC: H01L27/11582 ,  H01L29/10 ,  G11C16/14 ,  G11C16/04 ,  G11C16/10 ,  H01L29/267

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a channel structure extending in a direction perpendicular to the substrate; a charge storage structure disposed to be in contact with the channel structure; and a cell electrode structure disposed to be in contact with the charge storage structure in a lateral direction, wherein the channel structure comprises a hole conduction layer and an electron conduction layer.