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    MULTI-PHASE HIGH-PRECISION CURRENT SHARING CONTROL METHOD APPLIED TO CONSTANT ON-TIME CONTROL
    21.
    发明公开
    MULTI-PHASE HIGH-PRECISION CURRENT SHARING CONTROL METHOD APPLIED TO CONSTANT ON-TIME CONTROL 审中-公开

    公开(公告)号：US20240266943A1

    公开(公告)日：2024-08-08

    申请号：US18641384

    申请日：2024-04-21

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Shen XU ,  Haiqing ZHANG ,  Yujie LIU ,  Ruizhi WANG ,  Yuan GAO ,  Yongjia LI ,  Weifeng SUN ,  Longxing SHI

    IPC: H02M1/08 ,  H02M1/00 ,  H02M3/158

    CPC classification number: H02M1/082 ,  H02M1/0025 ,  H02M3/1586

    Abstract: A multi-phase high-precision current sharing control method applied to constant on-time control is provided, wherein a current difference between continuously sampled current of each line and mean current is processed by a PI compensation module and a low-pass filter module to obtain on-time regulation data. A high bit of the regulation data controls the value of counter reference Vref in an on-time control module, and a low bit controls the length of an enabled delay line in a delay line module. The counter timing control of the on-time control module is combined with the delay line timing control of the delay line module to improve the control precision of a DPWM. The method takes COT control of a Buck converter as a typical application. Compared with a multi-phase COT controller without a current-sharing mechanism, the method can improve the stability and reliability of the system.

    HIGH-THRESHOLD POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    22.
    发明申请
    HIGH-THRESHOLD POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20220367716A1

    公开(公告)日：2022-11-17

    申请号：US17762929

    申请日：2021-01-20

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Siyang LIU ,  Weifeng SUN ,  Chi ZHANG ,  Shuxuan XIN ,  Shen LI ,  Le QIAN ,  Chen GE ,  Longxing SHI

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/812 ,  H01L29/778

    Abstract: The present invention discloses a high-threshold power semiconductor device and a manufacturing method thereof. The high-threshold power semiconductor device includes, in sequence from bottom to top: a metal drain electrode, a substrate, a buffer layer, and a drift region; further including: a composite column body which is jointly formed by a drift region protrusion, a columnar p-region and a columnar n-region on the drift region, a channel layer, a passivation layer, a dielectric layer, a heavily doped semiconductor layer, a metal gate electrode and a source metal electrode. The composite column body is formed by sequentially depositing a p-type semiconductor layer and an n-type semiconductor layer on the drift region and then etching same. The channel layer and the passivation layer are formed in sequence by deposition. Thus, the above devices are divided into a cell region and a terminal region. The dielectric layer, the heavily doped semiconductor layer, the metal gate electrode and the source metal electrode only exist in the cell region, and the passivation layer of the terminal region extends upwards and is wrapped outside the channel layer. This structure can increase a threshold voltage of the device, improve the blocking characteristics of the device and reduce the size of a gate capacitance.

    LATERAL INSULATED GATE BIPOLAR TRANSISTOR WITH LOW TURN-ON OVERSHOOT CURRENT
    23.
    发明申请
    LATERAL INSULATED GATE BIPOLAR TRANSISTOR WITH LOW TURN-ON OVERSHOOT CURRENT 有权

    公开(公告)号：US20220157975A1

    公开(公告)日：2022-05-19

    申请号：US17606216

    申请日：2020-03-31

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Jing ZHU ,  Ankang LI ,  Long ZHANG ,  Weifeng SUN ,  Shengli LU ,  Longxing SHI

    IPC: H01L29/739 ,  H01L29/10

    Abstract: A lateral insulated gate bipolar transistor (IGBT) with a low turn-on overshoot current is provided to reduce a peak value of a current flowing through a device during turn-on of a second gate pulse while preventing a current capability and a withstand voltage capability from being degraded. The lateral IGBT includes: a buried oxygen arranged on a P-type substrate, an N-type drift region arranged on the buried oxygen, on which a P-type body region and an N-type buffer region are arranged, a P-type collector region arranged in the N-type buffer region, a field oxide layer arranged above the N-type drift region, a P-type well region arranged in the P-type body region, and a P-type emitter region and an emitter region arranged in the P-type well region, where inner boundaries of the foregoing 4 regions are synchronously recessed to form a pinch-off region. A gate oxide layer is arranged on a surface of the P-type body region, and a polysilicon gate is arranged on the gate oxide layer. The polysilicon gate includes a first gate located above the surface of the P-type body region and a second gate located above the pinch-off region and the N-type drift region. The first gate is connected to a first gate resistor, and the second gate is connected to a second gate resistor.

    ULTRA LOW-POWER NEGATIVE MARGIN TIMING MONITORING METHOD FOR NEURAL NETWORK CIRCUIT
    24.
    发明申请
    ULTRA LOW-POWER NEGATIVE MARGIN TIMING MONITORING METHOD FOR NEURAL NETWORK CIRCUIT 有权

    公开(公告)号：US20210174184A1

    公开(公告)日：2021-06-10

    申请号：US17181595

    申请日：2021-02-22

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Weiwei SHAN ,  Ziyu LI ,  Jun YANG ,  Longxing SHI

    IPC: G06N3/063 ,  G06N3/04

    Abstract: The present invention discloses an ultralow-power negative margin timing monitoring method of a neural network circuit, relates to an adaptive voltage regulation technology based on on-chip timing detection, and belongs to the technical field of low-power design of integrated circuit. The present invention provides an ultralow-power operating method of neural network circuit. By inserting a timing monitoring unit in specific position of critical paths and setting partial circuits to operate under “negative margin”, the system can further lower voltage, compress the timing slack, and obtain higher power gain.

    ULTRA-LOW-POWER SPEECH FEATURE EXTRACTION CIRCUIT BASED ON NON-OVERLAPPING FRAMING AND SERIAL FFT
    28.
    发明申请
    ULTRA-LOW-POWER SPEECH FEATURE EXTRACTION CIRCUIT BASED ON NON-OVERLAPPING FRAMING AND SERIAL FFT 有权

    公开(公告)号：US20220189459A1

    公开(公告)日：2022-06-16

    申请号：US17181908

    申请日：2021-02-22

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Weiwei SHAN ,  Lixuan ZHU ,  Jun YANG ,  Longxing SHI

    IPC: G10L15/02 ,  G10L25/24 ,  G06F17/14

    Abstract: The present invention discloses an ultra-low-power speech feature extraction circuit based on non-overlapping framing and serial fast Fourier transform (FFT), and belongs to the technical field of computation, calculation or counting. The circuit is oriented to the field of intelligence, and is integrally composed of a pre-process module, a windowing module, a Fourier transform module, a Mel filtering module, an adjacent frame merging module, a discrete cosine transform (DCT) module and other modules by optimizing the architecture of a Mel-frequency Cepstral Coefficients (MFCC) algorithm. Large-scale storage caused by framing is avoided in a non-overlapping framing mode, storage contained in the MFCC algorithm is further reduced, and the circuit area and the power consumption are greatly reduced. An FFT algorithm in the feature extraction circuit adopts a serial pipeline mode to process data, makes full use of the characteristics of serial inflow of audio data, and further reduces the storage area and operations of the circuit.

    GRAPHENE CHANNEL SILICON CARBIDE POWER SEMICONDUCTOR TRANSISTOR
    29.
    发明申请
    GRAPHENE CHANNEL SILICON CARBIDE POWER SEMICONDUCTOR TRANSISTOR 有权

    公开(公告)号：US20210336009A1

    公开(公告)日：2021-10-28

    申请号：US16486494

    申请日：2018-09-25

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Weifeng SUN ,  Siyang LIU ,  Lizhi TANG ,  Sheng LI ,  Chi ZHANG ,  Jiaxing WEI ,  Shengli LU ,  Longxing SHI

    IPC: H01L29/16 ,  H01L29/06 ,  H01L29/78

    Abstract: The invention provides a graphene channel silicon carbide power semiconductor transistor, and its cellular structure thereof. Characterized in that, a graphene strip serving as a channel is embedded in a surface of the P-type body region and two ends of the graphene strip are respectively contacted with a boundary between the N+-type source region and the P-type body region and a boundary between the P-type body region and the N-type drift region, and the graphene strip is distributed in a cellular manner in a gate width direction, a conducting channel of a device is still made of graphene; in the case of maintaining basically invariable on-resistance and current transmission capacity, the P-type body regions are separated by the graphene strip, thus enhancing a function of assisting depletion, which further reduces an overall off-state leakage current of the device, and improves a breakdown voltage.

    BI-DIRECTIONAL ADAPTIVE CLOCKING CIRCUIT SUPPORTING A WIDE FREQUENCY RANGE
    30.
    发明申请
    BI-DIRECTIONAL ADAPTIVE CLOCKING CIRCUIT SUPPORTING A WIDE FREQUENCY RANGE 有权

    公开(公告)号：US20210313975A1

    公开(公告)日：2021-10-07

    申请号：US16957724

    申请日：2019-07-09

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Weiwei SHAN ,  Jun YANG ,  Longxing SHI

    IPC: H03K5/14 ,  H03K5/131 ,  G04F10/00

    Abstract: A two-way adaptive clock circuit supporting a wide frequency range is composed of a phase clock generating module, a phase clock selecting module, an adaptive clock stretching or compressing amount regulating circuit module and a control module. The adaptive clock stretching or compressing amount regulating circuit module can monitor delay information of a critical path in a chip in real time and feed the information back into the control module. After receiving a clock stretching or compressing enable signal and a stretching or compressing scale signal, the control module selects a target phase clock from clocks generated by the phase clock generating module to rapidly regulate an adaptive clock in a current cycle. The present invention is applied to an adaptive voltage frequency regulating circuit based on on-line time sequence monitoring.

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