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公开(公告)号：US10186491B2
公开(公告)日：2019-01-22
申请号：US15606212
申请日：2017-05-26
Inventor： Sébastien Petitdidier , Mathieu Lisart
IPC: H01L23/00 , H01L21/768 , H01L23/522
Abstract: An integrated circuit chip includes an interconnection stack with a cavity formed therein. The cavity extends through one or more interconnection levels of the stack. A material at least partially fills the cavity. The fill material has a selectivity to polishing and/or to etching different by more than 10% from a selectivity to polishing and/or to etching of a material forming an insulator of the interconnection stack.
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公开(公告)号：US10177101B2
公开(公告)日：2019-01-08
申请号：US15596767
申请日：2017-05-16
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Christian Rivero , Pascal Fornara , Guilhem Bouton , Mathieu Lisart
IPC: H01L23/00 , H01L21/311 , H01L23/528 , H01L27/088 , H01L23/522 , H01L23/58 , H01L21/768
Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.
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公开(公告)号：US20180102328A1
公开(公告)日：2018-04-12
申请号：US15606212
申请日：2017-05-26
Inventor： Sébastien Petitdidier , Mathieu Lisart
IPC: H01L23/00 , H01L23/522 , H01L21/768
CPC classification number: H01L23/573 , H01L21/76802 , H01L21/76831 , H01L23/522 , H01L23/5226
Abstract: An integrated circuit chip includes an interconnection stack with a cavity formed therein. The cavity extends through one or more interconnection levels of the stack. A material at least partially fills the cavity. The fill material has a selectivity to polishing and/or to etching different by more than 10% from a selectivity to polishing and/or to etching of a material forming an insulator of the interconnection stack.
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公开(公告)号：US09935062B2
公开(公告)日：2018-04-03
申请号：US15661369
申请日：2017-07-27
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Mathieu Lisart , Nicolas Borrel
CPC classification number: H01L23/576 , G01R31/2851 , G01R31/44 , G06F21/6245 , H01L22/34 , H01L23/647 , H03K17/687
Abstract: An integrated circuit including a plurality of first semiconductor strips of a first conductivity type and of second semiconductor strips of a second conductivity type arranged in alternated and contiguous fashion on a region of the second conductivity type, including for each of the first strips: a plurality of bias contacts; for each bias contact, a switch capable of applying a potential on the bias contact; two detection contacts arranged at the ends of the first strip; and a detection circuit having its activation causing the turning off of the switches and the comparison with a threshold of the resistance between the detection contacts.
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公开(公告)号：US20180040574A1
公开(公告)日：2018-02-08
申请号：US15789362
申请日：2017-10-20
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Alexandre Sarafianos , Mathieu Lisart , Jimmy Fort
IPC: H01L23/00 , H01L21/762
CPC classification number: H01L23/576 , H01L21/762 , H01L27/088
Abstract: An electronic chip including: a plurality of first semiconductor bars of a first conductivity type and of second semiconductor bars of a second conductivity type arranged alternately and contiguously on a region of the first conductivity type; two detection contacts arranged at the ends of each second bar; a circuit for detecting the resistance between the detection contacts of each second bar; insulating trenches extending in the second bars down to a first depth between circuit elements; and insulating walls extending across the entire width of each second bar down to a second depth greater than the first depth.
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Patent Agency Ranking
公开(公告)号：US09224701B2
公开(公告)日：2015-12-29
申请号：US14667232
申请日：2015-03-24
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Mathieu Lisart , Sylvie Wuidart , Alexandre Sarafianos
CPC classification number: H01L23/576 , G06F21/75 , H01L22/14 , H01L22/30 , H01L22/34 , H01L2924/0002 , Y10T307/76 , H01L2924/00
Abstract: An integrated circuit, including: a semiconductor substrate of a first conductivity type; a plurality of regions of the first conductivity type vertically extending from the surface of the substrate, each of the regions being laterally delimited all along its periphery by a region of the second conductivity type; and a device for detecting a variation of the substrate resistance between each region of the first conductivity type and an area for biasing the substrate to a reference voltage.
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公开(公告)号：US20140111230A1
公开(公告)日：2014-04-24
申请号：US13654991
申请日：2012-10-18
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Mathieu Lisart , Thierry Soude
IPC: G01R27/08
CPC classification number: G01R27/08 , G01R31/2856 , G01R31/311 , G01R31/31719 , G09C1/00 , H01L23/576 , H01L2924/0002 , H04L9/004 , H04L2209/12 , H01L2924/00
Abstract: A system for detecting a laser attack on an integrated circuit chip formed in a semiconductor substrate, including a detection device capable of detecting voltage variations of the substrate.
Abstract translation: 一种用于检测形成在半导体衬底中的集成电路芯片上的激光攻击的系统，包括能够检测衬底的电压变化的检测装置。
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28.发明申请公开(公告)号：US20130015900A1
公开(公告)日：2013-01-17
申请号：US13625697
申请日：2012-09-24
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Mathieu Lisart , Fabrice Marinet
CPC classification number: G06F1/26 , G06F21/72 , G06K19/07309 , H01L21/76224 , H01L23/576 , H01L2924/0002 , H03K3/84 , H03K19/003 , H04L9/004 , H04L2209/12 , Y10T29/49155 , H01L2924/00
Abstract: The disclosure relates to a countermeasure method in an electronic microcircuit, comprising successive process phases executed by a circuit of the microcircuit, and adjusting a power supply voltage between power supply and ground terminals of the circuit, as a function of a random value generated for the process phase, at each process phase executed by the circuit.
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公开(公告)号：US12063775B2
公开(公告)日：2024-08-13
申请号：US18484906
申请日：2023-10-11
Inventor： Abderrezak Marzaki , Mathieu Lisart , Benoit Froment
CPC classification number: H10B20/367 , G11C16/0466 , H01L23/57
Abstract: The present description concerns a ROM including at least one first rewritable memory cell. In an embodiment, a method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells is proposed. Each of the plurality of memory cells includes a rewritable first transistor and a rewritable second transistor. An insulated gate of the rewritable first transistor is connected to an insulated gate of the rewritable second transistor. The method includes successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well-formed between an associated first insulating layer and the semiconductor structure, and wherein the rewritable first insulating layer is in direct contact with the semiconductor structure; and successively depositing a second insulating layer and a second gate layer.
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公开(公告)号：US20240040781A1
公开(公告)日：2024-02-01
申请号：US18484906
申请日：2023-10-11
Inventor： Abderrezak Marzaki , Mathieu Lisart , Benoit Froment
IPC: H10B20/00
CPC classification number: H10B20/367 , H01L23/57
Abstract: The present description concerns a ROM including at least one first rewritable memory cell. In an embodiment, a method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells is proposed. Each of the plurality of memory cells includes a rewritable first transistor and a rewritable second transistor. An insulated gate of the rewritable first transistor is connected to an insulated gate of the rewritable second transistor. The method includes successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well-formed between an associated first insulating layer and the semiconductor structure, and wherein the rewritable first insulating layer is in direct contact with the semiconductor structure; and successively depositing a second insulating layer and a second gate layer.
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