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    BURIED SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME
    23.
    发明申请
    BURIED SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME 有权
    用于集成电路晶体管器件的引出源漏极触点及其制造方法

    公开(公告)号：US20160284599A1

    公开(公告)日：2016-09-29

    申请号：US15179620

    申请日：2016-06-10

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

    Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai ,  William J. Taylor

    IPC: H01L21/8234 ,  H01L21/285 ,  H01L21/84

    CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

    Abstract: An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filled with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

    Abstract translation: 在基板上形成集成电路晶体管。 衬底中的沟槽至少部分地被金属材料填充以形成埋在衬底中的源极（或漏极）触点。 衬底还包括与源极（或漏极）接触电连接的衬底中的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底可以是绝缘体上硅（SOI）或体积型。 埋入的源极（或漏极）接触器使用与源极（或漏极）和沟道区域在基底的相同水平处提供的接点，使得与源极（或漏极）区域的一侧电连接。

    Method for making semiconductor device with different fin sets
    24.
    发明授权
    Method for making semiconductor device with different fin sets 有权
    制造具有不同翅片组的半导体器件的方法

    公开(公告)号：US09299721B2

    公开(公告)日：2016-03-29

    申请号：US14280998

    申请日：2014-05-19

    Applicant: STMICROELECTRONICS, INC ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh ,  Kejia Wang ,  Daniel Chanemougame

    IPC: H01L21/30 ,  H01L27/12 ,  H01L29/66

    CPC classification number: H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795

    Abstract: A method for making a semiconductor device may include forming, above a substrate, first and second semiconductor regions laterally adjacent one another and each including a first semiconductor material. The first semiconductor region may have a greater vertical thickness than the second semiconductor region and define a sidewall with the second semiconductor region. The method may further include forming a spacer above the second semiconductor region and adjacent the sidewall, and forming a third semiconductor region above the second semiconductor region and adjacent the spacer, with the second semiconductor region including a second semiconductor material different than the first semiconductor material. The method may also include removing the spacer and portions of the first semiconductor material beneath the spacer, forming a first set of fins from the first semiconductor region, and forming a second set of fins from the second and third semiconductor regions.

    Abstract translation: 制造半导体器件的方法可以包括在衬底上方形成彼此横向相邻并且包括第一半导体材料的第一和第二半导体区域。 第一半导体区域可以具有比第二半导体区域更大的垂直厚度并且限定具有第二半导体区域的侧壁。 该方法还可以包括在第二半导体区域的上方形成并邻近侧壁的间隔物，以及在第二半导体区域上方并邻近间隔物形成第三半导体区域，其中第二半导体区域包括与第一半导体材料不同的第二半导体材料 。 该方法还可以包括在间隔物下面移除间隔物和第一半导体材料的部分，从第一半导体区域形成第一组散热片，以及从第二和第三半导体区域形成第二组散热片。

    Semiconductor device including vertically spaced semiconductor channel structures and related methods
    25.
    发明授权
    Semiconductor device including vertically spaced semiconductor channel structures and related methods 有权
    半导体器件包括垂直间隔的半导体通道结构和相关方法

    公开(公告)号：US09263338B2

    公开(公告)日：2016-02-16

    申请号：US14060874

    申请日：2013-10-23

    Applicant: STMicroelectronics, Inc. ,  GLOBALFOUNDRIES INC.

    Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie

    IPC: H01L21/00 ,  H01L21/8234 ,  H01L27/088

    CPC classification number: H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/0886

    Abstract: A method for making a semiconductor device may include forming, on a substrate, at least one stack of alternating first and second semiconductor layers. The first semiconductor layer may comprise a first semiconductor material and the second semiconductor layer may comprise a second semiconductor material. The first semiconductor material may be selectively etchable with respect to the second semiconductor material. The method may further include removing portions of the at least one stack and substrate to define exposed sidewalls thereof, forming respective spacers on the exposed sidewalls, etching recesses through the at least one stack and substrate to define a plurality of spaced apart pillars, selectively etching the first semiconductor material from the plurality of pillars leaving second semiconductor material structures supported at opposing ends by respective spacers, and forming at least one gate adjacent the second semiconductor material structures.

    Abstract translation: 制造半导体器件的方法可以包括在衬底上形成交替的第一和第二半导体层的至少一个叠层。 第一半导体层可以包括第一半导体材料，第二半导体层可以包括第二半导体材料。 第一半导体材料可以相对于第二半导体材料可选择性地蚀刻。 该方法还可以包括去除至少一个堆叠和衬底的部分以限定其暴露的侧壁，在暴露的侧壁上形成相应的间隔物，蚀刻通过至少一个堆叠和衬底的凹槽以限定多个间隔开的柱，选择性蚀刻 来自多个柱的第一半导体材料离开第二半导体材料结构，在相对端通过相应的间隔件支撑，并且形成与第二半导体材料结构相邻的至少一个栅极。

    METHOD OF FORMING A REDUCED RESISTANCE FIN STRUCTURE
    27.
    发明申请
    METHOD OF FORMING A REDUCED RESISTANCE FIN STRUCTURE 有权
    形成降低电阻结构的方法

    公开(公告)号：US20150364578A1

    公开(公告)日：2015-12-17

    申请号：US14307011

    申请日：2014-06-17

    Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh ,  Xiuyu Cai ,  Kejia Wang

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/20

    CPC classification number: H01L29/66795 ,  H01L29/20 ,  H01L29/205 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

    Abstract: Methods and structures for forming a reduced resistance region of a finFET are described. According to some aspects, a dummy gate and first gate spacer may be formed above a fin comprising a first semiconductor composition. At least a portion of source and drain regions of the fin may be removed, and a second semiconductor composition may be formed in the source and drain regions in contact with the first semiconductor composition. A second gate spacer may be formed covering the first gate spacer. The methods may be used to form finFETs having reduced resistance at source and drain junctions.

    Abstract translation: 描述了形成finFET的电阻减小区域的方法和结构。 根据一些方面，可以在包括第一半导体组合物的鳍片之上形成伪栅极和第一栅极间隔物。 可以去除鳍的源区和漏区的至少一部分，并且可以在与第一半导体组合物接触的源区和漏区中形成第二半导体组合物。 可以形成覆盖第一栅极间隔物的第二栅极间隔物。 该方法可用于形成在源极和漏极结处具有降低的电阻的finFET。

    BURIED SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME
    29.
    发明申请
    BURIED SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME 有权
    用于集成电路晶体管器件的引出源漏极触点及其制造方法

    公开(公告)号：US20150357425A1

    公开(公告)日：2015-12-10

    申请号：US14297822

    申请日：2014-06-06

    Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai ,  William J. Taylor

    IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

    Abstract: An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

    Abstract translation: 在基板上形成集成电路晶体管。 衬底中的沟槽至少部分地与金属材料填充以形成埋在衬底中的源极（或漏极）接触。 衬底还包括与源极（或漏极）接触电连接的衬底中的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底可以是绝缘体上硅（SOI）或体积型。 埋入的源极（或漏极）接触器使用与源极（或漏极）和沟道区域在基底的相同水平处提供的接点，使得与源极（或漏极）区域的一侧电连接。

    FinFETs and techniques for controlling source and drain junction profiles in finFETs
    30.
    发明授权
    FinFETs and techniques for controlling source and drain junction profiles in finFETs 有权
    FinFET和用于控制finFET中的源极和漏极结型材的技术

    公开(公告)号：US09202919B1

    公开(公告)日：2015-12-01

    申请号：US14447685

    申请日：2014-07-31

    Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Kejia Wang ,  Chun-chen Yeh

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848

    Abstract: Techniques and structures for shaping the source and drain junction profiles of a finFET are described. A fin may be partially recessed at the source and drain regions of the finFET. The partially recessed fin may be further recessed laterally and vertically, such that the laterally recessed portion extends under at least a portion of the finFET's gate structure. Source and drain regions of the finFET may be formed by growing a buffer layer on the etched surfaces of the fin and/or growing a source and drain layer at the source and drain regions of the fin. The lateral recess can improve channel-length uniformity along the height of the fin.

    Abstract translation: 描述了用于成形finFET的源极和漏极结线廓的技术和结构。 翅片可以部分地凹陷在finFET的源极和漏极区域。 部分凹入的翅片可以进一步侧向和垂直地凹入，使得横向凹入部分在finFET的栅极结构的至少一部分下方延伸。 可以通过在鳍的蚀刻表面上生长缓冲层和/或在鳍的源极和漏极区生长源极和漏极层来形成鳍FET的源区和漏极区。 横向凹槽可以改善沿翅片高度的通道长度均匀性。

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