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公开(公告)号：US11374111B2
公开(公告)日：2022-06-28
申请号：US16743293
申请日：2020-01-15
发明人： Xiuyu Cai , Chun-Chen Yeh , Qing Liu , Ruilong Xie
IPC分类号： H01L29/78 , H01L29/66 , H01L29/417 , H01L29/06 , H01L21/768 , H01L29/08 , H01L29/161 , H01L29/165
摘要： A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.
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公开(公告)号：US10749031B2
公开(公告)日：2020-08-18
申请号：US15273778
申请日：2016-09-23
发明人： Xiuyu Cai , Qing Liu , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L29/78 , H01L29/417 , H01L29/66 , H01L29/08 , H01L29/45 , H01L21/02 , H01L21/8234 , H01L21/768 , H01L21/285
摘要： A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.
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3.发明授权公开(公告)号：US10355020B2
公开(公告)日：2019-07-16
申请号：US15180860
申请日：2016-06-13
发明人： Qing Liu , Xiuyu Cai , Ruilong Xie , Chun-chen Yeh
IPC分类号： H01L27/12 , H01L29/417 , H01L29/66 , H01L21/8234 , H01L21/28 , H01L29/06 , H01L29/10 , H01L29/78 , G06N3/04 , G10L15/16 , H01L29/36
摘要： Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.
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公开(公告)号：US09922883B2
公开(公告)日：2018-03-20
申请号：US15180158
申请日：2016-06-13
发明人： Xiuyu Cai , Qing Liu , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L27/12 , H01L21/8238 , H01L29/08 , H01L29/786 , H01L21/84 , H01L21/768 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/76895 , H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0847 , H01L29/7842 , H01L29/7848 , H01L29/786 , H01L29/78684
摘要： A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states.
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公开(公告)号：US09748352B2
公开(公告)日：2017-08-29
申请号：US14984688
申请日：2015-12-30
发明人： Qing Liu , Ruilong Xie , Chun-chen Yeh , Xiuyu Cai
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78 , H01L29/16 , H01L29/06 , H01L29/51 , H01L29/66 , H01L29/167 , H01L29/36 , H01L29/10 , H01L29/161 , H01L29/165 , B82Y10/00 , H01L29/775 , H01L29/786
CPC分类号： H01L29/42392 , B82Y10/00 , H01L29/0649 , H01L29/0673 , H01L29/1037 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/42364 , H01L29/51 , H01L29/518 , H01L29/66439 , H01L29/66545 , H01L29/66742 , H01L29/6681 , H01L29/775 , H01L29/785 , H01L29/78618 , H01L29/78696
摘要： A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wraparound gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.
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公开(公告)号：US09620505B2
公开(公告)日：2017-04-11
申请号：US15073100
申请日：2016-03-17
发明人： Qing Liu , Xiuyu Cai , Ruilong Xie , Chun-chen Yeh , Kejia Wang , Daniel Chanemougame
IPC分类号： H01L21/30 , H01L27/088 , H01L27/12 , H01L29/66 , H01L21/84 , H01L29/06 , H01L29/161
CPC分类号： H01L27/0886 , H01L21/845 , H01L27/1211 , H01L29/0649 , H01L29/161 , H01L29/66795
摘要： A semiconductor device which includes: a substrate; a first set of fins above the substrate of a first semiconductor material; a second set of fins above the substrate and of a second semiconductor material different than the first semiconductor material; and an isolation region positioned between the first and second sets of fins, the isolation region having a nitride layer. The isolation region may be an isolation pillar or an isolation trench.
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公开(公告)号：US09564501B2
公开(公告)日：2017-02-07
申请号：US14581741
申请日：2014-12-23
发明人： Qing Liu , Xiuyu Cai , Ruilong Xie , Chun-chen Yeh
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78 , H01L29/66 , H01L29/40
CPC分类号： H01L29/4236 , H01L29/401 , H01L29/42364 , H01L29/42384 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66772 , H01L29/66795 , H01L29/7825 , H01L29/78654
摘要： The present disclosure is directed to a gate structure for a transistor. The gate structure is formed on a substrate and includes a trench. There are sidewalls that line the trench. The sidewalls have a first dimension at a lower end of the trench and a second dimension at an upper end of the trench. The first dimension being larger than the second dimension, such that the sidewalls are tapered from a lower region to an upper region. A high k dielectric liner is formed on the sidewalls and a conductive liner is formed on the high k dielectric liner. A conductive material is in the trench and is adjacent to the conductive liner. The conductive material has a first dimension at the lower end of the trench that is smaller than a second dimension at the upper end of the trench.
摘要翻译： 本公开涉及晶体管的栅极结构。 栅极结构形成在衬底上并且包括沟槽。 有沟槽划线的侧壁。 侧壁在沟槽的下端具有第一尺寸，在沟槽的上端具有第二尺寸。 第一尺寸大于第二尺寸，使得侧壁从下部区域向上部区域逐渐变细。 在侧壁上形成高k电介质衬垫，并且在高k电介质衬垫上形成导电衬垫。 导电材料在沟槽中并且与导电衬垫相邻。 导电材料在沟槽的下端具有小于沟槽上端的第二尺寸的第一尺寸。
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公开(公告)号：US09502518B2
公开(公告)日：2016-11-22
申请号：US14312418
申请日：2014-06-23
发明人： Qing Liu , Ruilong Xie , Chun-chen Yeh , Xiuyu Cai
IPC分类号： H01L29/423 , H01L29/78 , H01L29/16 , H01L29/06 , H01L29/51 , H01L29/66 , H01L29/167 , H01L29/36 , H01L29/10 , H01L29/161 , H01L29/165 , B82Y10/00 , H01L29/775 , H01L29/786
CPC分类号： H01L29/42392 , B82Y10/00 , H01L29/0649 , H01L29/0673 , H01L29/1037 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/42364 , H01L29/51 , H01L29/518 , H01L29/66439 , H01L29/66545 , H01L29/66742 , H01L29/6681 , H01L29/775 , H01L29/785 , H01L29/78618 , H01L29/78696
摘要： A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wrap-around gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.
摘要翻译： 描述了一种高性能GAA FET，其中垂直堆叠的硅纳米线在传统的FinFET晶体管中承载与鳍片基本上相同的驱动电流，但是在较低的工作电压下并且具有更高的可靠性。 在现有的纳米线GAA FET中出现的一个问题是，当使用金属来形成环绕栅极时，在源极和漏极区域之间以及在通道下方的金属栅极部分可以产生短路。 然而，本文所述的垂直堆叠的纳米线器件在形成栅极之前通过形成与源极和漏极区域接触的绝缘屏障来避免这种短路。 通过使用牺牲膜，制造工艺几乎完全自对准，使得仅需要一个光刻掩模层，这显着降低制造成本。
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公开(公告)号：US20160276348A1
公开(公告)日：2016-09-22
申请号：US15168382
申请日：2016-05-31
发明人： Xiuyu Cai , Qing Liu , Ruilong Xie , Chun-chen Yeh
IPC分类号： H01L27/092 , H01L29/165 , H01L21/8238
CPC分类号： H01L27/0924 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/0922 , H01L27/1211 , H01L29/0684 , H01L29/1054 , H01L29/16 , H01L29/165 , H01L29/7849
摘要： A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.
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公开(公告)号：US09287130B1
公开(公告)日：2016-03-15
申请号：US14676345
申请日：2015-04-01
发明人： Xiuyu Cai , Ajey Poovannummoottil Jacob , Ruilong Xie , Bruce Doris , Kangguo Cheng , Jason R. Cantone , Sylvie Mignot , David Moreau , Muthumanickam Sankarapandian , Pierre Morin , Su Chen Fan , Kisik Choi , Murat K. Akarvardar
IPC分类号： H01L21/00 , H01L21/308 , H01L21/8234 , H01L21/265 , H01L21/266
CPC分类号： H01L21/823431 , H01L21/30604 , H01L21/845 , H01L29/66795
摘要： A method includes forming a plurality of fin elements above a substrate. A mask is formed above the substrate. The mask has an opening defined above at least one selected fin element of the plurality of fin elements. An ion species is implanted into the at least one selected fin element through the opening to increase its etch characteristics relative to the other fin elements. The at least one selected fin element is removed selectively relative to the other fin elements.
摘要翻译： 一种方法包括在基底上形成多个翅片元件。 在基板上形成掩模。 掩模具有限定在多个翅片元件中的至少一个选定翅片元件上方的开口。 通过开口将离子物质注入到至少一个选定的翅片元件中，以相对于其它翅片元件增加其蚀刻特性。 选择性地将至少一个选定的翅片元件相对于其它翅片元件移除。
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