公开(公告)号：US10665497B2

公开(公告)日：2020-05-26

申请号：US15457447

申请日：2017-03-13

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS Inc

Inventor： Emmanuel Augendre ,  Nicolas Loubet ,  Sylvain Maitrejean ,  Pierre Morin

IPC: H01L21/20 ,  H01L21/762 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L21/18 ,  H01L29/16 ,  H01L21/8238 ,  H01L29/161

Abstract: The method of manufacturing a structure comprising one or several strained semiconducting zones capable of forming one or several transistor channel regions, the method including the following steps: a) providing a substrate coated with a masking layer wherein there are one or several first slits exposing one or several first oblong semiconducting portions made of a first semiconducting material and extending in a first direction, b) making a second semiconducting material grow with a mesh parameter different from the mesh parameter of the first semiconducting material, so as to form one or several first semiconducting blocks strained along the first direction, on said one or several first oblong semiconducting portions.

公开(公告)号：US20200083376A1

公开(公告)日：2020-03-12

申请号：US16680222

申请日：2019-11-11

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/165 ,  H01L29/66

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

公开(公告)号：US10418488B2

公开(公告)日：2019-09-17

申请号：US15677855

申请日：2017-08-15

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/786

Abstract: Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer.

公开(公告)号：US10205022B2

公开(公告)日：2019-02-12

申请号：US14939729

申请日：2015-11-12

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Pierre Morin

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L27/088 ,  H01L21/02 ,  H01L29/06

Abstract: A method of making a semiconductor device includes forming a first spacer for at least one gate stack on a first semiconductor material layer, and forming a respective second spacer for each of source and drain regions adjacent the at least one gate. Each second spacer has a pair of opposing sidewalls and an end wall coupled thereto. The method includes filling the source and drain regions with a second semiconductor material while the first and second spacers provide confinement.

公开(公告)号：US10037922B2

公开(公告)日：2018-07-31

申请号：US15874813

申请日：2018-01-18

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Pierre Morin ,  Yann Mignot

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/78

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

公开(公告)号：US20170200653A1

公开(公告)日：2017-07-13

申请号：US15469851

申请日：2017-03-27

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin ,  Yann Mignot

IPC: H01L21/8238 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/7842 ,  H01L29/785

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

公开(公告)号：US20170154900A1

公开(公告)日：2017-06-01

申请号：US15432492

申请日：2017-02-14

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Pierre Morin

IPC: H01L27/12 ,  H01L29/10 ,  H01L21/3105 ,  H01L29/06 ,  H01L21/84 ,  H01L21/308 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02592 ,  H01L21/02598 ,  H01L21/02694 ,  H01L21/3081 ,  H01L21/31051 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).

公开(公告)号：US09252208B1

公开(公告)日：2016-02-02

申请号：US14447678

申请日：2014-07-31

Applicant: STMicroelectronics, Inc. ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives ,  GLOBALFOUNDRIES Inc.

Inventor： Pierre Morin ,  Maud Vinet ,  Laurent Grenouillet ,  Ajey Poovannummoottil Jacob

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0607 ,  H01L21/02636 ,  H01L21/283 ,  H01L21/3086 ,  H01L21/32 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/1066 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.

公开(公告)号：US09166049B2

公开(公告)日：2015-10-20

申请号：US14201555

申请日：2014-03-07

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Nicolas Loubet ,  Ali Khakifirooz ,  Pierre Morin ,  Sanjay C. Mehta

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods and structures for increasing strain in fully insulated finFETs are described. The finFET structures may be formed on an insulating layer and include source, channel, and drain regions that are insulated all around. During fabrication, the source and drain regions may be formed as suspended structures. A strain-inducing material may be formed around the source and drain regions on four contiguous sides so as to impart strain to the channel region of the finFET.

Abstract translation: 描述了在全绝缘finFET中增加应变的方法和结构。 finFET结构可以形成在绝缘层上，并且包括绝缘的源极，沟道和漏极区域。 在制造期间，源区和漏区可以形成为悬挂结构。 应变诱导材料可以在四个相邻侧面上的源极和漏极区域周围形成，以便对finFET的沟道区域施加应力。

公开(公告)号：US09099559B2

公开(公告)日：2015-08-04

申请号：US14027758

申请日：2013-09-16

Applicant: STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L21/70 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

Abstract translation: 描述形成应变通道鳍状FET的方法和结构。 可以使用在体基板上生长的不同晶格常数的两个外延层来形成finFET的鳍结构。 可以切割第一薄的应变外延层以形成用于翅片的应变消除的基础结构。 基础结构可以被约束在应变消除状态。 翅片结构可以在基底结构上的第二层中外延生长。 受限的碱基结构可以在外延生长的翅片中形成比在非约束基础结构中发生的更大量的应变。