中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

46 records (took 0.02 seconds)

    Nonvolatile memory device having cell-over-periphery (COP) structure with address re-mapping
    22.
    发明授权
    Nonvolatile memory device having cell-over-periphery (COP) structure with address re-mapping 有权

    公开(公告)号：US11467932B2

    公开(公告)日：2022-10-11

    申请号：US16865948

    申请日：2020-05-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

    IPC: G11C16/10 ,  G06F11/20 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11556 ,  H01L27/11582

    Abstract: A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

    Memory device
    23.
    发明授权
    Memory device 有权

    公开(公告)号：US11437105B2

    公开(公告)日：2022-09-06

    申请号：US17234955

    申请日：2021-04-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yohan Lee ,  Sangwan Nam ,  Sangwon Park

    IPC: G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/04 ,  G11C16/32 ,  G11C16/08 ,  G11C16/30

    Abstract: A memory device includes memory blocks, each including memory cells, and peripheral circuits that control the memory blocks and execute an erase operation for each of the memory blocks. Each memory block includes word lines stacked on a substrate, channel structures extending perpendicular to an upper surface of the substrate and penetrating through the word lines, and a source region disposed on the substrate and connected to the channel structures. During an erase operation in which an erase voltage is input to the source region of a target memory block, the peripheral circuits reduce a voltage of a first word line from a first bias voltage to a second bias voltage at a first time and reduce a voltage of a second word line, different from the first word line, from a third bias voltage to a fourth bias voltage at a second time different from the first in time.

    Nonvolatile memory device and method of controlling initialization of the same
    24.
    发明授权
    Nonvolatile memory device and method of controlling initialization of the same 有权

    公开(公告)号：US11056200B2

    公开(公告)日：2021-07-06

    申请号：US17012135

    申请日：2020-09-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jiyeon Shin ,  Sangwan Nam ,  Sangwon Park

    IPC: G11C7/00 ,  G11C16/34 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/1157 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11556 ,  G11C16/10 ,  H01L27/11582

    Abstract: Method of controlling initialization of nonvolatile memory device, where nonvolatile memory device includes memory cell region including first metal pad and peripheral circuit region including second metal pad and vertically connected to memory cell region by first and second metal pads, includes performing first sensing operation to sense write setting data stored in first memory cells in memory cell region of first memory plane and store first read setting data in first page buffer circuit in peripheral circuit region of first memory plane, performing second sensing operation to sense write setting data stored in second memory cells in memory cell region of second memory plane and store second read setting data in second page buffer circuit in peripheral circuit region of second memory plane and performing dump-down operation to store restored setting data in buffer based on first read setting data and second read setting data.

    Non-volatile memory device for detecting defects of bit lines and word lines
    25.
    发明授权
    Non-volatile memory device for detecting defects of bit lines and word lines 有权

    公开(公告)号：US12131798B2

    公开(公告)日：2024-10-29

    申请号：US17972300

    申请日：2022-10-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junyoung Ko ,  Sangwan Nam ,  Youse Kim ,  Heewon Kim

    IPC: G11C7/10 ,  G06F11/10

    CPC classification number: G11C7/1057 ,  G06F11/1076

    Abstract: Provided is a non-volatile memory device. The non-volatile memory device includes: a memory cell array including cell strings, each including memory cells respectively connected to word lines; a page buffer circuit including page buffers respectively connected to the memory cells through bit lines, wherein a first page buffer is connected to a first cell string through a first bit line; a control logic circuit configured to control a pre-sensing operation to disconnect the first bit line and the first cell string from each other during a pre-sensing period for detecting a defect of the first bit line and control a post-sensing operation to connect the first bit line and the first cell string to each other in a post-sensing period for detecting defects of the word lines and the first bit line; and a defect detection circuit configured to detect defects of the word lines based the sensing operations.

    MEMORY DEVICES
    30.
    发明申请
    MEMORY DEVICES 有权

    公开(公告)号：US20230123297A1

    公开(公告)日：2023-04-20

    申请号：US17863697

    申请日：2022-07-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byungsoo Kim ,  Sangwan Nam ,  MinJae Seo ,  Bongsoon Lim

    IPC: H01L27/11575 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582

    Abstract: A memory device includes a first cell array region and a second cell array region separated by a separation region, each including at least one memory block having a plurality of gate electrode layers stacked in a first direction. The gate electrode layers include an upper select electrode layer including a plurality of string select lines, and a first electrode layer including a plurality of first word lines arranged below the string select lines. The first word lines include a first connection line to connect first end portions of the first word lines positioned on the opposite side of the separation region to each other and a plurality of second connection lines to connect some of second end portions of the plurality of first word lines adjacent to the separation region to each other, wherein each of the second connection lines is shorter than the first connection line.

Patent Agency Ranking