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    Systems and methods for detecting intra-chip communication errors in a reconfigurable hardware system
    23.
    发明授权
    Systems and methods for detecting intra-chip communication errors in a reconfigurable hardware system 有权

    公开(公告)号：US11994938B2

    公开(公告)日：2024-05-28

    申请号：US17716988

    申请日：2022-04-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yukui Luo ,  Andrew Chang

    IPC: G06F11/07

    CPC classification number: G06F11/079 ,  G06F11/0745

    Abstract: Systems and methods for error detection for an address channel are disclosed. The method includes generating a token, applying the token to a request at a source, and generating a first result. The request with the first result is transmitted to a destination over the address channel. A determination is made, at the destination, whether an error associated with the request has occurred. The determining whether the error has occurred includes: receiving a received request corresponding to the request over the address channel; receiving the first result with the received request; applying the token to the received request and generating a second result; comparing the first result with the second result; and transmitting a signal in response to the comparing.

    SYSTEMS AND METHODS FOR DATA COMPARISON
    25.
    发明公开
    SYSTEMS AND METHODS FOR DATA COMPARISON 审中-公开

    公开(公告)号：US20240020307A1

    公开(公告)日：2024-01-18

    申请号：US18091852

    申请日：2022-12-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Praveen Krishnamoorthy ,  Changho Choi ,  Andrew Chang

    IPC: G06F16/245

    CPC classification number: G06F16/24569

    Abstract: A method includes receiving, at a hardware circuit of a device, a target value corresponding to a target data. The method further includes outputting, from the hardware circuit, a first indicator that source data corresponds to the target value. The method further includes, based on the first indicator, outputting, from software executing at the device, a result indicator that the source data corresponds to the target data.

    IN-MEMORY COMPUTING WITH CACHE COHERENT PROTOCOL
    26.
    发明申请
    IN-MEMORY COMPUTING WITH CACHE COHERENT PROTOCOL 有权

    公开(公告)号：US20230069786A1

    公开(公告)日：2023-03-02

    申请号：US18045332

    申请日：2022-10-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Krishna T. Malladi ,  Andrew Chang

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0817 ,  G06F13/16 ,  G06F13/42

    Abstract: A system for computing. In some embodiments, the system includes: a memory, the memory including one or more function-in-memory circuits; and a cache coherent protocol interface circuit having a first interface and a second interface. A function-in-memory circuit of the one or more function-in-memory circuits may be configured to perform an operation on operands including a first operand retrieved from the memory, to form a result. The first interface of the cache coherent protocol interface circuit may be connected to the memory, and the second interface of the cache coherent protocol interface circuit may be configured as a cache coherent protocol interface on a bus interface.

    SYSTEM WITH CACHE-COHERENT MEMORY AND SERVER-LINKING SWITCH
    29.
    发明申请
    SYSTEM WITH CACHE-COHERENT MEMORY AND SERVER-LINKING SWITCH 有权

    公开(公告)号：US20210311900A1

    公开(公告)日：2021-10-07

    申请号：US17026074

    申请日：2020-09-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Krishna Teja Malladi ,  Andrew Chang ,  Ehsan M. Najafabadi

    IPC: G06F13/40 ,  G06F9/4401 ,  G06F15/173

    Abstract: A system and method for managing memory resources. In some embodiments the system includes a first server, a second server, and a server-linking switch connected to the first server and to the second server. The first server may include a stored-program processing circuit, a cache-coherent switch, and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, the cache-coherent switch is connected to the server-linking switch, and the stored-program processing circuit is connected to the cache-coherent switch.

    IN-MEMORY COMPUTING WITH CACHE COHERENT PROTOCOL
    30.
    发明申请
    IN-MEMORY COMPUTING WITH CACHE COHERENT PROTOCOL 有权

    公开(公告)号：US20210311739A1

    公开(公告)日：2021-10-07

    申请号：US16914129

    申请日：2020-06-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Krishna T. Malladi ,  Andrew Chang

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0817 ,  G06F13/16 ,  G06F13/42

    Abstract: A system for computing. In some embodiments, the system includes: a memory, the memory including one or more function-in-memory circuits; and a cache coherent protocol interface circuit having a first interface and a second interface. A function-in-memory circuit of the one or more function-in-memory circuits may be configured to perform an operation on operands including a first operand retrieved from the memory, to form a result. The first interface of the cache coherent protocol interface circuit may be connected to the memory, and the second interface of the cache coherent protocol interface circuit may be configured as a cache coherent protocol interface on a bus interface.

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