公开(公告)号：US11574692B2

公开(公告)日：2023-02-07

申请号：US17359688

申请日：2021-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwangho Choi ,  Jin-Young Kim ,  Se Hwan Park ,  Il Han Park ,  Ji-Sang Lee ,  Joonsuc Jang

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.

公开(公告)号：US11127465B2

公开(公告)日：2021-09-21

申请号：US16934150

申请日：2020-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Sang Lee

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34 ,  G11C7/22 ,  G11C29/04

Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop.

公开(公告)号：US10056152B2

公开(公告)日：2018-08-21

申请号：US15493326

申请日：2017-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wook-Ghee Hahn ,  Ji-Sang Lee

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C16/3427 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  G11C16/349 ,  G11C2211/563 ,  H01L27/11582

Abstract: In a method of reading data in a nonvolatile memory device including a plurality of memory cells arranged at intersections of a plurality of word-lines and a plurality of bit-lines, a read request on a first word-line of the plurality of word-lines is received, a read operation is performed on a second word-line adjacent to the first word-line and a read operation is performed on the first word-line based on data read from memory cells of the second word-line. The read operation on the first word-line is performed by adjusting a level of recover read voltage applied to the first word-line during the read operation of the first word-line based on at least one of a program state of the data read from memory cells of the second word-line and an operating parameter of the nonvolatile memory device.

公开(公告)号：US09183924B2

公开(公告)日：2015-11-10

申请号：US14712939

申请日：2015-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Sang Lee ,  Moosung Kim ,  Kihwan Choi

IPC: G11C29/00 ,  G11C11/56 ,  G11C16/34 ,  G06F11/10

CPC classification number: G11C11/5635 ,  G06F11/1048 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/02 ,  G11C16/0483 ,  G11C16/3413 ,  G11C16/3436 ,  G11C16/3454 ,  G11C29/04 ,  G11C2029/0411 ,  G11C2211/5621

Abstract: Methods of operating nonvolatile memory devices may include identifying one or more multi-bit nonvolatile memory cells in a nonvolatile memory device that have undergone unintentional programming from an erased state to an at least partially programmed state. Errors generated during an operation to program a first plurality of multi-bit nonvolatile memory cells may be detected by performing a plurality of reading operations to generate error detection data and then decoding the error detection data to identify specific cells having errors. A programmed first plurality of multi-bit nonvolatile memory cells and a force-bit data vector, which was modified during the program operation, may be read to support error detection. This data, along with data read from a page buffer associated with the first plurality of multi-bit nonvolatile memory cells, may then be decoded to identify which of the first plurality of multi-bit nonvolatile memory cells are unintentionally programmed cells.

公开(公告)号：US09007839B2

公开(公告)日：2015-04-14

申请号：US13915688

申请日：2013-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Sang Lee ,  Moosung Kim

IPC: G11C11/34 ,  G11C16/26 ,  G11C11/56 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/3454 ,  G11C16/3495 ,  G11C2211/5641

Abstract: A method of reading a nonvolatile memory device comprises applying a read voltage to a memory cell array to read selected memory cells, counting a number of the selected memory cells that have a threshold voltage higher or lower than the read voltage, and comparing the counted number with a reference value to determine a number of bits stored in the selected memory cells.

Abstract translation: 读取非易失性存储器件的方法包括将读取电压施加到存储器单元阵列以读取所选择的存储器单元，对具有高于或低于读取电压的阈值电压的所选存储单元的数量进行计数，以及将所计数的数目 具有用于确定存储在所选择的存储器单元中的位数的参考值。

公开(公告)号：US11574683B2

公开(公告)日：2023-02-07

申请号：US17402955

申请日：2021-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Sang Lee

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34 ,  G11C7/22 ,  G11C29/04

Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop.

公开(公告)号：US20190272878A1

公开(公告)日：2019-09-05

申请号：US16415274

申请日：2019-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Sang Lee

IPC: G11C16/10 ,  G11C16/24 ,  G11C16/08 ,  G11C16/34 ,  G11C16/32 ,  G11C16/04 ,  G11C16/26

Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop.

公开(公告)号：US10325658B2

公开(公告)日：2019-06-18

申请号：US15661386

申请日：2017-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Sang Lee

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34 ,  G11C7/22 ,  G11C29/04

Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop.

公开(公告)号：US09583197B2

公开(公告)日：2017-02-28

申请号：US15067751

申请日：2016-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Sang Lee

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427

Abstract: A nonvolatile memory device includes memory cells stacked in a direction perpendicular to a substrate and further includes a first memory cell string connected between a selected bit line and a selected string selection line, a second memory cell string connected between the selected bit line and an unselected string selection line, and a third memory cell string connected to an unselected bit line. During a bit line setup section of a program operation, a ground voltage is provided to the selected bit line and a power supply voltage provided to the unselected string selection line is changed to the ground voltage.

Abstract translation: 非易失性存储器件包括沿垂直于衬底的方向堆叠的存储器单元，并且还包括连接在所选位线和所选择的串选择线之间的第一存储单元串，连接在所选位线和未选择位线之间的第二存储单元串 串选择线，以及连接到未选位线的第三存储单元串。 在编程操作的位线设置部分期间，将地电压提供给所选择的位线，并且提供给未选择的串选择线的电源电压被改变为接地电压。