公开(公告)号：US20240072056A1

公开(公告)日：2024-02-29

申请号：US18334099

申请日：2023-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junggun You ,  Gigwan Park

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A semiconductor device includes first and second active fins on first and second regions of a substrate, an isolation pattern on a boundary between the first and second regions and portions of the first and second regions adjacent thereto and separating the first and second active fins, a first gate structure on the first active fin and the isolation pattern on the first region, a second gate structure on the second active fin and the isolation pattern on the second region, a first source/drain layer on the first active fin adjacent to the first gate structure, and a second source/drain layer on the second active fin adjacent to the second gate structure. A width of a portion of the first gate structure overlapping the first active fin is greater than that of a portion of the second gate structure overlapping the second active fin.

公开(公告)号：US11855209B2

公开(公告)日：2023-12-26

申请号：US17380256

申请日：2021-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggun You ,  Yoonjoong Kim ,  Seungwoo Do ,  Sungil Park

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L29/1033

Abstract: A semiconductor device including a substrate that includes first to third regions; a first channel structure on the first region and including first channel patterns that are vertically stacked on the substrate; a second channel structure on the second region and including a second channel pattern on the substrate; a third channel structure on the third region and including third channel patterns and fourth channel patterns that are vertically and alternately stacked on the substrate; first to third gate electrodes on the first to third channel structures; and first to third source/drain patterns on opposite sides of the first to third channel structures, wherein the first, second, and fourth channel patterns include a first semiconductor material, and the third channel patterns include a second semiconductor material different from the first semiconductor material.

公开(公告)号：US11515421B2

公开(公告)日：2022-11-29

申请号：US17205282

申请日：2021-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggun You ,  Joohee Jung ,  Jaehyeoung Ma ,  Namhyun Lee

IPC: H01L29/78 ,  H01L29/10 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device including a substrate having a central region and a peripheral region; an integrated circuit structure on the central region; and a first structure on the peripheral region and surrounding the central region, wherein a portion of the first structure includes a first fin structure defined by a device isolation region in the substrate; a first dielectric layer covering an upper surface and side surfaces of the first fin structure and an upper surface of the device isolation region; a first gate structure on the first fin structure, the first gate structure including a first gate conductive layer, a first gate dielectric layer covering lower and side surfaces of the first gate conductive layer, and first gate spacer layers on side walls of the first gate conductive layer; and a first insulating structure covering the first dielectric layer and the first gate structure.

公开(公告)号：US10256324B2

公开(公告)日：2019-04-09

申请号：US15664226

申请日：2017-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungil Park ,  Changhee Kim ,  Yunil Lee ,  Mirco Cantoro ,  Junggun You ,  Donghun Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/28 ,  H01L29/40 ,  H01L29/423

Abstract: A semiconductor device includes an active pillar on a substrate. A first source/drain region is disposed at a top end of the active pillar and has a greater width than the active pillar. A first insulating layer is disposed on a sidewall of the active pillar and a second insulating layer is disposed on at least a bottom surface of the first source/drain region. A gate electrode is disposed on the first insulating layer and the second insulating layer. A second source/drain region is disposed in the substrate at a bottom end of the active pillar. Methods of fabrication are also described.