公开(公告)号：US20210377080A1

公开(公告)日：2021-12-02

申请号：US17156813

申请日：2021-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaewoo PARK ,  Youngdon CHOI ,  Junghwan CHOI ,  Changsik YOO

IPC: H04L25/02 ,  H04L25/49 ,  H04L25/14

Abstract: Provided are a memory device and a memory system including the same. The memory device may include a data bus inversion (DBI) mode selector configured to select a first multi-bit DBI signal from among a plurality of multi-bit DBI signals respectively corresponding to a plurality of DBI modes according to multi-bit data; a multi-mode DBI encoder configured to generate encoded multi-bit data by DBI encoding the multi-bit data according to the first multi-bit DBI signal; and a transceiver configured to transmit a data symbol corresponding to the encoded multi-bit data through a data channel and transmit a DBI symbol corresponding to the first multi-bit DBI signal through a DBI channel.

公开(公告)号：US20190094196A1

公开(公告)日：2019-03-28

申请号：US16137026

申请日：2018-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin PARK ,  Byungchul KIM ,  Youngju LEE ,  Dongkyu CHOI ,  Junghwan CHOI ,  Seungku HAN

IPC: G01N33/00 ,  H04B17/391 ,  G01S7/48 ,  H04B17/10

Abstract: A method for identifying radio signal transmission characteristics in a wireless communication system and an apparatus therefor are provided. The method may include identifying a signal transmission site, identifying a signal reception site, finding an area where a tree is present between the signal transmission site and the signal reception site, checking characteristics of the crown of the tree and characteristics of the trunk of the tree, and examining transmission characteristics of a radio signal sent from the signal transmission site to the signal reception site on the basis of the characteristics of the crown and the trunk. The method and apparatus relate to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for internet of things (IoT), and may be applied to intelligent services based on the 5G communication and the IoT-related technologies.

公开(公告)号：US20240370386A1

公开(公告)日：2024-11-07

申请号：US18772354

申请日：2024-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungmin JIN ,  Jindo BYUN ,  Younghoon SON ,  Youngdon CHOI ,  Junghwan CHOI

IPC: G06F13/16 ,  H04L25/49

Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.

公开(公告)号：US20240187002A1

公开(公告)日：2024-06-06

申请号：US18350606

申请日：2023-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwook LEE ,  Joohwan KIM ,  Junyoung PARK ,  Jindo BYUN ,  Eunseok SHIN ,  Junghwan CHOI

IPC: H03L7/081 ,  G11C7/22 ,  H03K5/135

CPC classification number: H03L7/0812 ,  G11C7/222 ,  H03K5/135

Abstract: A semiconductor device includes a phase splitter configured to output a plurality of clock signals having different phases by using a plurality of external clock signals having different phases, a plurality of code generators configured to receive a pair of selection clock signals determined from the plurality of clock signals and to output a phase code corresponding to a phase difference error between the pair of selection clock signals, and a delay circuit configured to at least partly simultaneously adjust at least two of a rising edge and a falling edge of each of the plurality of external clock signals with reference to the phase code during a lock time.

公开(公告)号：US20240168091A1

公开(公告)日：2024-05-23

申请号：US18325162

申请日：2023-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ikjin JO ,  Jaewoo PARK ,  Jueon KIM ,  Myoungbo KWAK ,  Junghwan CHOI

IPC: G01R31/317 ,  G01R31/319

CPC classification number: G01R31/31727 ,  G01R31/31726 ,  G01R31/31926

Abstract: A transmitter includes a data generator, a serializer, a transmission driver and a feedback circuit. The data generator generates a retimed data signal and retimed test data by adjusting a delay amount of each of an input data signal and a test data based on adjusted clock signals. The serializer generates a serial data signal by serializing the retimed data signal based on multi-phase clock signals. The transmission driver generates an output data signal based on the serial data signal and transmits the output data signal through a channel. The feedback circuit detects the setup margin and the hold margin of the retimed test data through a separate path different from a path of the retimed data signal and generates the adjusted clock signals by adjusting delay amounts of the multi-phase clock signals based on the detected setup margin and hold margin of the retimed test data.

公开(公告)号：US20230353132A1

公开(公告)日：2023-11-02

申请号：US18219254

申请日：2023-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mingyu LEE ,  Youngchul CHO ,  Seungjin PARK ,  Youngdon CHOI ,  Junghwan CHOI

IPC: H03K5/06 ,  H03K5/05 ,  H03K5/15

CPC classification number: H03K5/06 ,  H03K5/05 ,  H03K5/1506 ,  H03K5/1508

Abstract: A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.

公开(公告)号：US20230171007A1

公开(公告)日：2023-06-01

申请号：US18096657

申请日：2023-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungmin JIN ,  Younghoon SON ,  Hyunyoon CHO ,  Youngdon CHOI ,  Junghwan CHOI

IPC: H04B17/19 ,  H04B17/18 ,  H04B17/00 ,  H04L7/00

CPC classification number: H04B17/19 ,  H04B17/18 ,  H04B17/0085 ,  H04L7/0016

Abstract: A translation device, a test system, and a memory system are provided. The translation device includes plural first input/output (I/O) circuits that respectively transmit and receive first signals through plural pins based on a pulse amplitude modulation (PAM)-M mode, a second I/O circuit that transmits and receives a second signal through one or more pins based on a PAM-N mode, and a translation circuit that translates the first signals into the second signal and translates the second signal into the first signals. M and N are different integers of 2 or more.

公开(公告)号：US20220385287A1

公开(公告)日：2022-12-01

申请号：US17751148

申请日：2022-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung PARK ,  Joohwan KIM ,  Jindo BYUN ,  Eunseok SHIN ,  Hyunyoon CHO ,  Youngdon CHOI ,  Junghwan CHOI

IPC: H03K17/693 ,  H03K19/20

Abstract: A transmitter circuit includes a clock generator configured to generate a plurality of clock signals having different phases, and a plurality of selection circuits configured to receive a plurality of parallel data signals and output a serial data signal on an output node based on the plurality of clock signals and the received plurality of parallel data signals. Each of the plurality of selection circuits includes a data multiplexer configured to generate a plurality of data selection signals based on the received one of the plurality of parallel data signals and the plurality of clock signals; a control signal generator configured to generate first and second control signals based on the plurality of data selection signals; and an output driver connected to the output node, and configured to precharge the output node based on the first control signal or discharge the output node based on the second control signal.

公开(公告)号：US20220068356A1

公开(公告)日：2022-03-03

申请号：US17223458

申请日：2021-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwangseob SHIN ,  Jindo BYUN ,  Younghoon SON ,  Youngdon CHOI ,  Junghwan CHOI

IPC: G11C11/4091 ,  G11C11/4099 ,  G11C11/4076 ,  G11C11/4074 ,  G11C11/408

Abstract: A multi-level signal receiver includes a data sampler circuit and a reference voltage generator circuit. The data sampler includes (M−1) sense amplifiers which compare a multi-level signal having one of M voltage levels different from each other with (M−1) reference voltages. The data sampler generates a target data signal including N bits, M is an integer greater than two and N is an integer greater than one. The reference voltage generator generates the (M−1) reference voltages, At least two sense amplifiers of the (M−1) sense amplifiers have different sensing characteristics.

公开(公告)号：US20240250689A1

公开(公告)日：2024-07-25

申请号：US18494340

申请日：2023-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongmin KO ,  Jaewoo PARK ,  Myoungbo KWAK ,  Jueon KIM ,  Junghwan CHOI

IPC: H03M1/06

CPC classification number: H03M1/0604

Abstract: An analog-to-digital conversion circuit includes an analog-to-digital converter (ADC) configured to receive an input signal and a first clock signal from an external source and to output a second clock signal and a digital output signal, a decision counter configured to increment a decision count value each time when the second clock signal received from the analog-to-digital converter is applied to the decision counter, a voltage control logic configured to output a control signal based on a result of comparing the decision count value with a reference count value, and a regulator configured to output an operation voltage, wherein the ADC is configured to adjust the cycle of the second clock signal, and the voltage control logic is configured to control the regulator to output a corrected operating voltage via the control signal.