公开(公告)号：US11508815B2

公开(公告)日：2022-11-22

申请号：US16928508

申请日：2020-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun Lee ,  Minsu Seol ,  Yeonchoo Cho ,  Hyeonjin Shin

IPC: H01L29/10 ,  H01L21/02 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Provided is a semiconductor device which use a two-dimensional semiconductor material as a channel layer. The semiconductor device includes: a gate electrode on a substrate; a gate dielectric on the gate electrode; a channel layer on the gate dielectric; and a source electrode and a drain electrode that may be electrically connected to the channel layer. The gate dielectric has a shape with a height greater than a width, and the channel layer includes a two-dimensional semiconductor material.

公开(公告)号：US11374171B2

公开(公告)日：2022-06-28

申请号：US16823865

申请日：2020-03-19

Applicant: Samsung Electronics Co., Ltd. ,  President and Fellows Of Harvard College

Inventor： Minhyun Lee ,  Dovran Amanov ,  Renjing Xu ,  Houk Jang ,  Haeryong Kim ,  Hyeonjin Shin ,  Yeonchoo Cho ,  Donhee Ham

IPC: H01L45/00 ,  H01L27/24

Abstract: Provided are memristors and neuromorphic devices including the memristors. A memristor includes a lower electrode and an upper electrode that are apart from each other and first and second two-dimensional material layers that are arranged between the lower electrode and the upper electrode and stacked without a chemical bond therebetween.

公开(公告)号：US11189699B2

公开(公告)日：2021-11-30

申请号：US16428006

申请日：2019-05-31

Applicant: Samsung Electronics Co., Ltd. ,  THE UNIVERSITY OF CHICAGO ,  Center for Technology Licensing at Cornell University

Inventor： Minhyun Lee ,  Jiwoong Park ,  Saien Xie ,  Jinseong Heo ,  Hyeonjin Shin

IPC: H01L29/15 ,  H01L29/10

Abstract: Provided are a superlattice structure including a two-dimensional material and a device including the superlattice structure. The superlattice structure may include at least two different two-dimensional (2D) materials bonded to each other in a lateral direction, and an interfacial region of the at least two 2D materials may be strained. The superlattice structure may have a bandgap adjusted by the interfacial region that is strained. The at least two 2D materials may include first and second 2D materials. The first 2D material may have a first bandgap in an intrinsic state thereof. The second 2D material may have a second bandgap in an intrinsic state thereof. An interfacial region of the first and second 2D materials and an adjacent region may have a third bandgap between the first bandgap and the second bandgap.

公开(公告)号：US10996556B2

公开(公告)日：2021-05-04

申请号：US16004585

申请日：2018-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun Lee ,  Hyeonjin Shin ,  Seongjun Jeong ,  Seongjun Park

IPC: G03F1/62 ,  G03F1/64

Abstract: A pellicle configured to protecting a photomask from external contaminants may include a metal catalyst layer and a pellicle membrane including a 2D material on the metal catalyst layer, wherein the metal catalyst layer supports edge regions of the pellicle membrane and does not support a central region of the pellicle membrane. The metal catalyst layer may be on a substrate, such that the substrate and the metal catalyst layer collectively support the edge region of the pellicle membrane and do not support the central region of the pellicle membrane. The pellicle may be formed based on growing the 2D material on the metal catalyst layer and etching an inner region of the metal catalyst layer that supports the central region of the formed pellicle membrane.

公开(公告)号：US10460935B2

公开(公告)日：2019-10-29

申请号：US15817979

申请日：2017-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun Lee ,  Hyeonjin Shin ,  Jaeho Lee ,  Haeryong Kim

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L29/778 ,  H01L29/06 ,  H01L29/24 ,  H01L29/41 ,  H01L29/16

Abstract: An electronic device includes first and second electrodes that are spaced apart from each other and a 2D material layer. The 2D material layer connects the first and second electrodes. The 2D material layer includes a plurality of 2D nanomaterials. At least some of the 2D nanomaterials overlap one another.

公开(公告)号：US09515144B2

公开(公告)日：2016-12-06

申请号：US14747243

申请日：2015-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun Lee ,  Jaeho Lee ,  Jin-seong Heo ,  Kiyoung Lee

IPC: H01L29/16 ,  H01L29/786 ,  H01L29/423 ,  H01L29/778 ,  H01L29/06 ,  H01L29/165 ,  H01L29/417

CPC classification number: H01L29/1606 ,  H01L29/0665 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/42356 ,  H01L29/778 ,  H01L29/78642 ,  H01L29/78684 ,  H01L29/78696

Abstract: Example embodiments relate to a fin-type graphene device. The fin-type graphene device includes a substrate, a graphene channel layer substantially vertical to the substrate, a gate insulating layer that covers one side surface of the graphene channel layer, a gate electrode on the gate insulating layer, and a source electrode and a drain electrode that are formed separately from each other on other side surface of the graphene channel layer.

Abstract translation: 示例性实施例涉及翅片型石墨烯装置。 翅片型石墨烯装置包括基板，基本上垂直于基板的石墨烯通道层，覆盖石墨烯通道层的一个侧表面的栅极绝缘层，栅极绝缘层上的栅电极以及源极和 漏电极，其在石墨烯通道层的另一侧表面上彼此分开形成。

公开(公告)号：US20250017017A1

公开(公告)日：2025-01-09

申请号：US18439308

申请日：2024-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoseok Heo ,  Kyunghun Kim ,  Sunho Kim ,  Hyungyung Kim ,  Minhyun Lee ,  Seokhoon Choi ,  Seungdam Hyun

IPC: H10B43/35 ,  H01L29/423

Abstract: A vertical NAND flash memory device and an electronic apparatus including the same are provided. The vertical NAND flash memory device includes a plurality of cell arrays. Each of the plurality of cell arrays includes a channel layer, a charge trap layer, and a plurality of gate electrodes provided on the charge trap layer. The charge trap layer includes a matrix including amorphous metal oxynitride and nanocrystals dispersed in the matrix and including nitride having semiconductor characteristics.

公开(公告)号：US20240221832A1

公开(公告)日：2024-07-04

申请号：US18328192

申请日：2023-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seyun KIM ,  Kyunghun Kim ,  Sunho Kim ,  Hyungyung Kim ,  Seungyeul Yang ,  Gukhyon Yon ,  Minhyun Lee ,  Joonsuk Lee ,  Seokhoon Choi ,  Hoseok Heo

IPC: G11C16/04 ,  H01L29/16 ,  H01L29/18 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L29/1606 ,  H01L29/18 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes: a channel layer; a plurality of gate electrodes and a plurality of insulating layers being spaced apart from the channel layer and being alternately arranged; a charge trap layer between the channel layer and a gate electrode, and a charge tunneling layer between the channel layer and the charge trap layer.

公开(公告)号：US12002882B2

公开(公告)日：2024-06-04

申请号：US18157478

申请日：2023-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun Lee ,  Minsu Seol ,  Yeonchoo Cho ,  Hyeonjin Shin

IPC: H01L29/778 ,  H01L27/092 ,  H01L29/24 ,  H01L29/417 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7788 ,  H01L27/092 ,  H01L29/24 ,  H01L29/41741 ,  H01L29/7831 ,  H01L29/78642

Abstract: A vertical type transistor includes: a substrate; a first source/drain electrode layer provided on the substrate; a second source/drain electrode layer provided above the first source/drain electrode layer; a first gate electrode layer provided between the first and second source/drain electrode layers; a first gate insulating film passing through the first gate electrode layer; a hole passing through the second source/drain electrode layer, the first gate insulating film, and the first source/drain electrode layer; and a first channel layer provided on a lateral side of the hole, wherein the first channel layer may include a 2D semiconductor.

公开(公告)号：US11600774B2

公开(公告)日：2023-03-07

申请号：US17094121

申请日：2020-11-10

Applicant: Samsung Electronics Co., Ltd. ,  President and Fellows Of Harvard College

Inventor： Minhyun Lee ,  Houk Jang ,  Donhee Ham ,  Chengye Liu ,  Henry Julian Hinton ,  Haeryong Kim ,  Hyeonjin Shin

IPC: H01L45/00 ,  H01L27/24

Abstract: A nonvolatile memory device includes a resistance switching layer, a gate on the resistance switching layer, a gate oxide layer between the resistance switching layer and the gate, and a source and a drain, spaced apart from each other, on the resistance switching layer. A resistance value of the resistance switching layer is changed based on an illumination of light irradiated onto the resistance switching layer and is maintained as a changed resistance value.