公开(公告)号：US10651195B2

公开(公告)日：2020-05-12

申请号：US16168219

申请日：2018-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Byoung-Taek Kim ,  Tae Hun Kim ,  Dongkyun Seo ,  Junhee Lim

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/51 ,  H01L27/11556 ,  H01L27/11524

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.

公开(公告)号：US20190312052A1

公开(公告)日：2019-10-10

申请号：US16232549

申请日：2018-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGHWAN LEE ,  Changseok Kang ,  Yongseok Kim ,  Junhee Lim ,  Kohji Kanamori

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/28 ,  H01L21/311 ,  H01L29/423

Abstract: Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor memory device includes a plurality of electrode structures provided on a substrate and extending in parallel to each other in one direction and each including electrodes and insulating layers alternately stacked on the substrate, a plurality of vertical structures penetrating the plurality of electrode structures, and an electrode separation structure disposed between two of the plurality of electrode structures adjacent to each other. Each of the electrodes includes an outer portion adjacent to the electrode separation structure, and an inner portion adjacent to the plurality of vertical structures. A thickness of the outer portion is smaller than a thickness of the inner portion.

公开(公告)号：US12268042B2

公开(公告)日：2025-04-01

申请号：US17746247

申请日：2022-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Dongsoo Woo ,  Kyunghwan Lee

IPC: H01L21/00 ,  H10K10/50 ,  H10K19/00 ,  H10K85/20

Abstract: A variable resistance memory device including a stack including insulating sheets and conductive sheets, which are alternatingly stacked on a substrate, the stack including a vertical hole vertically penetrating therethrough, a bit line on the stack, a conductive pattern electrically connected to the bit line and vertically extending in the vertical hole, and a resistance varying layer between the conductive pattern and an inner side surface of the stack defining the vertical hole may be provided. The resistance varying layer may include a first carbon nanotube electrically connected to the conductive sheets, and a second carbon nanotube electrically connected to the conductive pattern.

公开(公告)号：US12249651B2

公开(公告)日：2025-03-11

申请号：US17741219

申请日：2022-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Dongsoo Woo ,  Kyunghwan Lee

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/417

Abstract: A semiconductor device includes: a channel; a gate structure on the channel; a first source/drain arranged at a first end of the channel and including a metal; a first tunable band-gap layer arranged between the channel and the first source/drain and having a band gap that changes according to stress; a first electrostrictive layer between the gate structure and the first tunable band-gap layer, the first electrostrictive layer having a property of being deformed based on and upon application of an electric field; and a second source/drain at a second end of the channel.

公开(公告)号：US20240397727A1

公开(公告)日：2024-11-28

申请号：US18658265

申请日：2024-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ilho Myeong ,  Yongseok Kim ,  Sangwoo Han

IPC: H10B51/20 ,  H01L25/065 ,  H01L29/78 ,  H10B51/10 ,  H10B80/00

Abstract: A semiconductor device includes: a gate line; a hole extending through the gate line; a channel layer extending lengthwise in a first direction in the hole; a ferroelectric layer arranged between the channel layer and the gate line and extending lengthwise in the first direction in the hole; and a multi-tunneling dielectric structure arranged between the ferroelectric layer and the gate line and extending lengthwise in the first direction in the hole, wherein the multi-tunneling dielectric structure includes: a first silicon oxide film contacting the gate line; a second silicon oxide film spaced apart from the first silicon oxide film in a second direction and contacting the ferroelectric layer, wherein the second direction crosses the first direction; and a silicon oxynitride film disposed between the first silicon oxide film and the second silicon oxide film.

公开(公告)号：US20240206149A1

公开(公告)日：2024-06-20

申请号：US18541791

申请日：2023-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjun Lee ,  Hyoseok Kim ,  Yongseok Kim

IPC: H10B12/00

CPC classification number: H10B12/20

Abstract: A semiconductor device includes a source line extending in a first horizontal direction on a substrate, a channel layer extending in a vertical direction perpendicular to an upper surface of the substrate, and including a first end, a second end opposite to the first end, and a channel layer sidewall connecting the first end with the second end, the first end being disposed on the source line, a trap layer disposed on the channel layer sidewall, a gate insulating layer disposed on an outer surface of the trap layer, a word line disposed on at least one sidewall of the gate insulating layer and extending in a second horizontal direction crossing the first horizontal direction, a drain area disposed on the second end of the channel layer and including a metal or metal nitride, and a bit line disposed on the drain area and extending in the first horizontal direction.

公开(公告)号：US11996457B2

公开(公告)日：2024-05-28

申请号：US17443553

申请日：2021-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Ilgweon Kim ,  Seokhan Park ,  Kyunghwan Lee ,  Jaeho Hong

IPC: H01L29/423 ,  H01L23/482 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L23/4828 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device includes a plurality of semiconductor structures disposed on a substrate, a first conductive pattern, a first conductive pattern, a gate insulation pattern, a second conductive pattern and a second impurity region. Each of the semiconductor structures includes a first semiconductor pattern that has a linear shape that extends in a first direction and second semiconductor patterns that protrude from an upper surface of the first semiconductor pattern in a vertical direction. The semiconductor structures are spaced apart from each other in a second direction perpendicular to the first direction. The first conductive pattern is formed between the first semiconductor patterns. The first impurity region is formed in an opening in the first semiconductor pattern adjacent to a first sidewall of the second semiconductor pattern. The first impurity region includes an impurity diffusion harrier pattern and a polysilicon pattern doped with impurities.

公开(公告)号：US20240119984A1

公开(公告)日：2024-04-11

申请号：US18544996

申请日：2023-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Hong ,  Hyuncheol Kim ,  Yongseok Kim ,  Ilgweon Kim ,  Hyeoungwon Seo ,  Sungwon Yoo ,  Kyunghwan Lee

IPC: G11C11/402 ,  G11C11/39 ,  H01L27/102 ,  H01L29/66 ,  H01L29/749

CPC classification number: G11C11/4023 ,  G11C11/39 ,  H01L27/1027 ,  H01L29/66363 ,  H01L29/749

Abstract: A semiconductor memory device according to the present inventive concept includes: a semiconductor substrate; a common source semiconductor layer doped with impurities of a first conductivity type on the semiconductor substrate; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer; and a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering an internal wall of a channel hole extending in a vertical direction, and a memory cell structure filling the channel hole. The memory cell structure includes a channel layer, which has the memory cell dielectric layer thereon and fills at least a portion of the channel hole, and a drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type, and filling some of an upper portion of the channel hole.

公开(公告)号：US20240064996A1

公开(公告)日：2024-02-22

申请号：US18170136

申请日：2023-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiheun Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Ilho Myeong ,  Daewon Ha

IPC: H10B51/20 ,  H10B51/10 ,  H01L23/528 ,  H01L29/51 ,  H01L29/78

CPC classification number: H10B51/20 ,  H10B51/10 ,  H01L23/5283 ,  H01L29/516 ,  H01L29/78391

Abstract: A semiconductor device includes first and second cell arrays. The first cell array includes a first gate electrode that extends in a vertical direction, a first channel pattern on a side surface of the first gate electrode, and a first bit line electrically connected to the first channel pattern. The second cell array includes a second gate electrode that extends in the vertical direction, a second channel pattern on a side surface of the second gate electrode, and a second bit line electrically connected to the second channel pattern. A first bit line pad is electrically connected to the first bit line and a second bit line pad is electrically connected to the second bit line. The first bit line pad is spaced apart from the second bit line pad with the first and second cell arrays therebetween.

公开(公告)号：US11887986B2

公开(公告)日：2024-01-30

申请号：US17503713

申请日：2021-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungwon Yoo ,  Yongseok Kim ,  Ilgweon Kim ,  Hyuncheol Kim ,  Hyeoungwon Seo ,  Kyunghwan Lee ,  Jaeho Hong

IPC: H01L27/12 ,  H01L25/065 ,  H01L21/84 ,  H01L27/13 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/13 ,  H01L24/08 ,  H01L2224/08145

Abstract: A semiconductor memory device is disclosed. The semiconductor memory device may include a data storage layer including data storage devices, an interconnection layer disposed on the data storage layer, and a selection element layer provided between the data storage layer and the interconnection layer. The interconnection layer may include bit lines extending in a first direction. The selection element layer may include a cell transistor connected between one of the data storage devices and one of the bit lines, and the cell transistor may include an active pattern and a word line, which crosses the active pattern and is extended in a second direction crossing the first direction.