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公开(公告)号：US09437302B2
公开(公告)日：2016-09-06
申请号：US14616309
申请日：2015-02-06
发明人： Tai-Yuan Tseng , Cynthia Hsu , Kwang Ho Kim
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/24 , G11C16/26 , G11C16/3459
摘要： A sense amplifier provides a state-dependent lockout to limit sensing to those bit lines that target a currently selected state for sensing. A sense amplifier scans program data prior to sensing at the verify levels corresponding to a plurality of states. When program data matches a currently selected state, the sense amplifier senses the bit line voltage during verification and writes the result to a data latch. The sense amplifier may write the result to a data latch for storing quick pass write data, in response to sensing at a low verify level for the selected state for example. When program data does not match the currently selected state, the sense amplifier skips sensing for the bit line. The sense amplifier locks out the bit line prior to sensing based on the program data.
摘要翻译： 读出放大器提供状态相关的锁定，以将感测限制到目标为当前选择的状态用于感测的那些位线。 感测放大器在对应于多个状态的验证电平进行感测之前扫描程序数据。 当程序数据与当前选择的状态相匹配时，读出放大器在验证期间感测位线电压，并将结果写入数据锁存器。 响应于针对例如选定状态的低验证电平的感测，读出放大器可将结果写入用于存储快速写入数据的数据锁存器。 当程序数据与当前选择的状态不匹配时，读出放大器跳过位线的检测。 读出放大器根据程序数据在感测之前锁定位线。
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公开(公告)号：US20160172045A1
公开(公告)日：2016-06-16
申请号：US14794242
申请日：2015-07-08
发明人： Pitamber Shukla , Henry Chin , Dana Lee , Cynthia Hsu
CPC分类号： G11C16/16 , G11C11/5628 , G11C16/0483 , G11C16/26 , G11C16/3431 , G11C16/3445 , G11C2211/5644
摘要： A non-volatile memory system mitigates the effects of open block reading by analyzing the un-programmed region of a block before programming to determine a potential for read disturbance. The system may determine a read count value associated with open block reading of the memory block and/or perform partial block erase verification. To mitigate the effects of open block read disturbance, the system performs partial block erase for the un-programmed region of the memory block and/or limits programming in the un-programmed region.
摘要翻译： 非易失性存储器系统通过在编程之前分析块的未编程区域来确定读取干扰的可能性来缓解开放块读取的影响。 系统可以确定与存储块的开放块读取相关联的读取计数值和/或执行部分块擦除验证。 为了减轻开放块读取干扰的影响，系统对存储器块的未编程区域执行部分块擦除和/或限制非编程区域中的编程。
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23.发明申请Techniques for Reducing Read Disturb in Partially Written Blocks of Non-Volatile Memory 有权减少非易失性存储器部分写入块中的读取干扰的技术公开(公告)号：US20160141046A1
公开(公告)日：2016-05-19
申请号：US14543660
申请日：2014-11-17
发明人： Anubhav Khandelwal , Dana Lee , Abhijeet Manohar , Henry Chin , Gautam Dusija , Daniel Tuers , Chris Avila , Cynthia Hsu
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/3418
摘要： Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for data read. In both cases, non-selected word lines that are unwritten or, in the case of finding the last written word line, may be unwritten are biased with a lower read-pass voltage then is typically used. The result of such reads can also be applied to an algorithm for finding the last written word by skipping a varying number of word lines. Performance in a last written page determination can also be improved by use of shorter bit line settling times than for a standard read.
摘要翻译： 呈现技术以减少部分写入的NAND型非易失性存储器块的读取干扰量，这两者都用于当确定块中的最后写入字线以及数据读取时。 在这两种情况下，通常使用未被写入的未选择字线，或者在找到最后写入的字线的情况下，可能未被写入的低通读出电压被偏置。 这种读取的结果也可以应用于通过跳过不同数量的字线来找到最后写入的字的算法。 通过使用比标准读取更短的位线建立时间，也可以改善最后写入的页面确定中的性能。
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公开(公告)号：US20150221348A1
公开(公告)日：2015-08-06
申请号：US14616289
申请日：2015-02-06
发明人： Tai-Yuan Tseng , Yenlung Li , Cynthia Hsu , Kwang Ho Kim , Man L. Mui
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/24 , G11C16/26 , G11C16/3459
摘要： A non-volatile memory includes an efficient data latch structure for programming bit lines using at least three programming levels. A sense amplifier includes a first data latch for controlling the voltage of a corresponding bit line, and a second static data latch with scan circuitry for performing logic operations on the program data and sense results. The sense amplifier scans low verify sense results with program data to generate reduced programming data. The reduced programming data is transferred out of the first data latch after sensing for all states and the program data is scanned to generate program enable/inhibit data which is stored in the first data latch. After setting the bit line to a program inhibit or program enable level, the reduced programming data is transferred back to the first data latch. The bit lines for reduced programming are then adjusted to the reduced programming level.
摘要翻译： 非易失性存储器包括用于使用至少三个编程级别对位线进行编程的有效数据锁存结构。 读出放大器包括用于控制相应位线的电压的第一数据锁存器和具有扫描电路的第二静态数据锁存器，用于对程序数据执行逻辑运算并感测结果。 读出放大器利用程序数据扫描低校验感应结果，以产生简化的编程数据。 在感测所有状态之后，将减少的编程数据从第一数据锁存器传送出去，并且扫描程序数据以产生存储在第一数据锁存器中的程序使能/禁止数据。 在将位线设置为程序禁止或程序使能电平之后，减小的编程数据被传送回第一数据锁存器。 然后，用于减少编程的位线被调整到降低的编程电平。
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25.发明授权Programming select gate transistors and memory cells using dynamic verify level 有权使用动态验证级别编程选择栅极晶体管和存储单元公开(公告)号：US08929142B2
公开(公告)日：2015-01-06
申请号：US13759303
申请日：2013-02-05
发明人： Yingda Dong , Cynthia Hsu , Masaaki Higashitani , Ken Oowada
CPC分类号： G11C16/3459 , G11C16/0425 , G11C16/3427 , G11C16/3454
摘要： Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage to a common level with the slower-programming transistors at the conclusion of the programming operation. For programming of memory cells to different target data states, an offset between the initial and final verify levels can be different for each data state. In one approach, the offset is greater for lower target data states. The increases in the dynamic verify voltage can be progressively smaller with each subsequent program-verify iteration of the programming operation. The start of the increase can be adapted to the programming progress or can be at a predetermined program-verify iteration.
摘要翻译： 通过使用在编程操作期间从初始电平增加到最终电平的动态验证电压，选择栅极晶体管和存储器单元的编程精度增加。 更慢的编程晶体管在慢速编程晶体管之前被锁定在编程之外，但是在编程操作结束时经历程序干扰，将其阈值电压增加到较慢编程晶体管的公共电平。 为了将存储器单元编程到不同的目标数据状态，初始和最终验证电平之间的偏移量对于每个数据状态可以是不同的。 在一种方法中，对于较低的目标数据状态，偏移量较大。 随着编程操作的每个后续程序验证迭代，动态验证电压的增加可以逐渐减小。 增加的开始可以适应于编程进度，或者可以在预定的程序验证迭代。
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26.发明授权Programming select gate transistors and memory cells using dynamic verify level 有权使用动态验证级别编程选择栅极晶体管和存储单元公开(公告)号：US08913432B2
公开(公告)日：2014-12-16
申请号：US14285878
申请日：2014-05-23
发明人： Yingda Dong , Cynthia Hsu , Masaaki Higashitani , Ken Oowada
CPC分类号： G11C16/3459 , G11C16/0425 , G11C16/3427 , G11C16/3454
摘要： Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage to a common level with the slower-programming transistors at the conclusion of the programming operation. For programming of memory cells to different target data states, an offset between the initial and final verify levels can be different for each data state. In one approach, the offset is greater for lower target data states. The increases in the dynamic verify voltage can be progressively smaller with each subsequent program-verify iteration of the programming operation. The start of the increase can be adapted to the programming progress or can be at a predetermined program-verify iteration.
摘要翻译： 通过使用在编程操作期间从初始电平增加到最终电平的动态验证电压，选择栅极晶体管和存储器单元的编程精度增加。 更慢的编程晶体管在慢速编程晶体管之前被锁定在编程之外，但是在编程操作结束时经历程序干扰，将其阈值电压增加到较慢编程晶体管的公共电平。 为了将存储器单元编程到不同的目标数据状态，初始和最终验证电平之间的偏移量对于每个数据状态可以是不同的。 在一种方法中，对于较低的目标数据状态，偏移量较大。 随着编程操作的每个后续程序验证迭代，动态验证电压的增加可以逐渐减小。 增加的开始可以适应于编程进度，或者可以在预定的程序验证迭代。
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27.发明申请Programming Select Gate Transistors And Memory Cells Using Dynamic Verify Level 有权使用动态验证级别编程选择栅极晶体管和存储单元公开(公告)号：US20140219027A1
公开(公告)日：2014-08-07
申请号：US13759303
申请日：2013-02-05
发明人： Yingda Dong , Cynthia Hsu , Masaaki Higashitani , Ken Oowada
IPC分类号： G11C16/34
CPC分类号： G11C16/3459 , G11C16/0425 , G11C16/3427 , G11C16/3454
摘要： Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage to a common level with the slower-programming transistors at the conclusion of the programming operation. For programming of memory cells to different target data states, an offset between the initial and final verify levels can be different for each data state. In one approach, the offset is greater for lower target data states. The increases in the dynamic verify voltage can be progressively smaller with each subsequent program-verify iteration of the programming operation. The start of the increase can be adapted to the programming progress or can be at a predetermined program-verify iteration.
摘要翻译： 通过使用在编程操作期间从初始电平增加到最终电平的动态验证电压，选择栅极晶体管和存储器单元的编程精度增加。 更慢的编程晶体管在慢速编程晶体管之前被锁定在编程之外，但是在编程操作结束时经历程序干扰，将其阈值电压增加到较慢编程晶体管的公共电平。 为了将存储器单元编程到不同的目标数据状态，初始和最终验证电平之间的偏移量对于每个数据状态可以是不同的。 在一种方法中，对于较低的目标数据状态，偏移量较大。 随着编程操作的每个后续程序验证迭代，动态验证电压的增加可以逐渐减小。 增加的开始可以适应于编程进度，或者可以在预定的程序验证迭代。
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28.发明申请NONVOLATILE MEMORY AND METHOD FOR IMPROVED PROGRAMMING WITH REDUCED VERIFY 有权非易失性存储器和用于改进编程的方法，具有降低的验证公开(公告)号：US20130279263A1
公开(公告)日：2013-10-24
申请号：US13925621
申请日：2013-06-24
发明人： Yingda Dong , Ken Oowada , Cynthia Hsu
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/04 , G11C16/10 , G11C16/3468
摘要： A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to respective target states by a staircase waveform. The memory states are demarcated by a set of increasing demarcation threshold values (V1, . . . , VN). Initially in the programming pass, the memory cells are verified relative to a test reference threshold value. This test reference threshold has a value offset past a designate demarcation threshold value Vi among the set by a predetermined margin. The overshoot of each memory cell when programmed past Vi, to be more or less than the margin can be determined. Accordingly, memory cells found to have an overshoot more than the margin are counteracted by having their programming rate slowed down in a subsequent portion of the programming pass so as to maintain a tighter threshold distribution.
摘要翻译： 非易失性存储器的一组存储器单元在编程通道中并行编程，其中通过阶梯波形具有从擦除状态到各个目标状态的最小验证步骤。 存储器状态由一组增加的分界阈值（V1，...，VN）划分。 最初在编程过程中，相对于测试参考阈值验证存储器单元。 该测试参考阈值具有超过设定中的指定分界阈值Vi的值偏移预定余量。 可以确定当经过Vi编程时每个存储单元的过冲大于或小于余量。 因此，发现超过裕度的超调的存储器单元的编程速率在编程通过的后续部分中变慢，以便保持更严格的阈值分布而被抵消。
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