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公开(公告)号：US09552882B2
公开(公告)日：2017-01-24
申请号：US14616289
申请日：2015-02-06
Applicant: SanDisk Technologies Inc.
Inventor： Tai-Yuan Tseng , Yenlung Li , Cynthia Hsu , Kwang Ho Kim , Man L Mui
CPC classification number: G11C16/10 , G11C11/5628 , G11C16/24 , G11C16/26 , G11C16/3459
Abstract: A non-volatile memory includes an data latch structure for programming bit lines using at least three programming levels. A sense amplifier includes a first data latch for controlling the voltage of a corresponding bit line, and a second static data latch with scan circuitry for performing logic operations on the program data and sense results. The sense amplifier scans low verify sense results with program data to generate reduced programming data. The reduced programming data is transferred out of the first data latch after sensing for all states and the program data is scanned to generate program enable/inhibit data which is stored in the first data latch. After setting the bit line to a program inhibit or program enable level, the reduced programming data is transferred back to the first data latch. The bit lines for reduced programming are then adjusted to the reduced programming level.
Abstract translation: 非易失性存储器包括用于使用至少三个编程电平对位线进行编程的数据锁存结构。 读出放大器包括用于控制相应位线的电压的第一数据锁存器和具有扫描电路的第二静态数据锁存器，用于对程序数据执行逻辑运算并感测结果。 读出放大器利用程序数据扫描低校验感应结果，以产生简化的编程数据。 在对所有状态进行感测之后，减少的编程数据被传送出第一数据锁存器，并且扫描程序数据以产生存储在第一数据锁存器中的程序使能/禁止数据。 在将位线设置为程序禁止或程序使能电平之后，减小的编程数据被传送回第一数据锁存器。 然后，用于减少编程的位线被调整到降低的编程电平。
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公开(公告)号：US09437302B2
公开(公告)日：2016-09-06
申请号：US14616309
申请日：2015-02-06
Applicant: SanDisk Technologies Inc.
Inventor： Tai-Yuan Tseng , Cynthia Hsu , Kwang Ho Kim
CPC classification number: G11C16/10 , G11C11/5628 , G11C16/24 , G11C16/26 , G11C16/3459
Abstract: A sense amplifier provides a state-dependent lockout to limit sensing to those bit lines that target a currently selected state for sensing. A sense amplifier scans program data prior to sensing at the verify levels corresponding to a plurality of states. When program data matches a currently selected state, the sense amplifier senses the bit line voltage during verification and writes the result to a data latch. The sense amplifier may write the result to a data latch for storing quick pass write data, in response to sensing at a low verify level for the selected state for example. When program data does not match the currently selected state, the sense amplifier skips sensing for the bit line. The sense amplifier locks out the bit line prior to sensing based on the program data.
Abstract translation: 读出放大器提供状态相关的锁定，以将感测限制到目标为当前选择的状态用于感测的那些位线。 感测放大器在对应于多个状态的验证电平进行感测之前扫描程序数据。 当程序数据与当前选择的状态相匹配时，读出放大器在验证期间感测位线电压，并将结果写入数据锁存器。 响应于针对例如选定状态的低验证电平的感测，读出放大器可将结果写入用于存储快速写入数据的数据锁存器。 当程序数据与当前选择的状态不匹配时，读出放大器跳过位线的检测。 读出放大器根据程序数据在感测之前锁定位线。
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公开(公告)号：US20150221348A1
公开(公告)日：2015-08-06
申请号：US14616289
申请日：2015-02-06
Applicant: SanDisk Technologies Inc.
Inventor： Tai-Yuan Tseng , Yenlung Li , Cynthia Hsu , Kwang Ho Kim , Man L. Mui
CPC classification number: G11C16/10 , G11C11/5628 , G11C16/24 , G11C16/26 , G11C16/3459
Abstract: A non-volatile memory includes an efficient data latch structure for programming bit lines using at least three programming levels. A sense amplifier includes a first data latch for controlling the voltage of a corresponding bit line, and a second static data latch with scan circuitry for performing logic operations on the program data and sense results. The sense amplifier scans low verify sense results with program data to generate reduced programming data. The reduced programming data is transferred out of the first data latch after sensing for all states and the program data is scanned to generate program enable/inhibit data which is stored in the first data latch. After setting the bit line to a program inhibit or program enable level, the reduced programming data is transferred back to the first data latch. The bit lines for reduced programming are then adjusted to the reduced programming level.
Abstract translation: 非易失性存储器包括用于使用至少三个编程级别对位线进行编程的有效数据锁存结构。 读出放大器包括用于控制相应位线的电压的第一数据锁存器和具有扫描电路的第二静态数据锁存器，用于对程序数据执行逻辑运算并感测结果。 读出放大器利用程序数据扫描低校验感应结果，以产生简化的编程数据。 在感测所有状态之后，将减少的编程数据从第一数据锁存器传送出去，并且扫描程序数据以产生存储在第一数据锁存器中的程序使能/禁止数据。 在将位线设置为程序禁止或程序使能电平之后，减小的编程数据被传送回第一数据锁存器。 然后，用于减少编程的位线被调整到降低的编程电平。
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公开(公告)号：US08908432B2
公开(公告)日：2014-12-09
申请号：US13755905
申请日：2013-01-31
Applicant: Sandisk Technologies, Inc.
Inventor： Teruhiko Kamei , Seungpil Lee , Siu Lung Chan , Kwang Ho Kim , Man Lung Mui
CPC classification number: G11C16/28
Abstract: Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria such as a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a memory plane. Within each zone, different bit line read voltages may be applied to different bit line groupings in order to compensate for systematic variations in bit line resistance between neighboring bit lines due to the use of multiple patterning lithography techniques such as spacer-based double patterning.
Abstract translation: 描述了用于补偿存储器单元感测期间位线电阻变化的方法。 位线电阻的变化可能会在同一芯片上面对芯片或平面到平面。 在一些实施例中，对于管芯上的每个管芯或存储器平面，可以基于诸如故障位数的感测标准来确定与多个区域相关联的多个位线读取电压。 多个区域中的每个区域可以与存储器平面内的存储器阵列区域相关联。 在每个区域内，可以将不同的位线读取电压施加到不同的位线分组，以便补偿相邻位线之间的位线电阻的系统变化，这是由于使用诸如基于间隔物的双重图案化的多重图案化光刻技术。
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公开(公告)号：US20150221391A1
公开(公告)日：2015-08-06
申请号：US14616309
申请日：2015-02-06
Applicant: SanDisk Technologies Inc.
Inventor： Tai-Yuan Tseng , Cynthia Hsu , Kwang Ho Kim
CPC classification number: G11C16/10 , G11C11/5628 , G11C16/24 , G11C16/26 , G11C16/3459
Abstract: A sense amplifier provides a state-dependent lockout to limit sensing to those bit lines that target a currently selected state for sensing. A sense amplifier scans program data prior to sensing at the verify levels corresponding to a plurality of states. When program data matches a currently selected state, the sense amplifier senses the bit line voltage during verification and writes the result to a data latch. The sense amplifier may write the result to a data latch for storing quick pass write data, in response to sensing at a low verify level for the selected state for example. When program data does not match the currently selected state, the sense amplifier skips sensing for the bit line. The sense amplifier locks out the bit line prior to sensing based on the program data.
Abstract translation: 读出放大器提供状态相关的锁定，以将感测限制到目标为当前选择的状态用于感测的那些位线。 感测放大器在对应于多个状态的验证电平进行感测之前扫描程序数据。 当程序数据与当前选择的状态相匹配时，读出放大器在验证期间感测位线电压，并将结果写入数据锁存器。 响应于针对例如选定状态的低验证电平的感测，读出放大器可将结果写入用于存储快速写入数据的数据锁存器。 当程序数据与当前选择的状态不匹配时，读出放大器跳过位线的检测。 读出放大器根据程序数据在感测之前锁定位线。
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Patent Agency Ranking
公开(公告)号：US20140133231A1
公开(公告)日：2014-05-15
申请号：US13755911
申请日：2013-01-31
Applicant: SANDISK TECHNOLOGIES, INC.
Inventor： Kwang Ho Kim , Fumiaki Toyama , Seungpil Lee , Masaaki Higashitani
IPC: G11C16/28
CPC classification number: G11C16/28
Abstract: Methods for compensating for variations in bit line resistance in non-volatile memories are described. In some embodiments, use of multiple patterning lithography for forming bit lines may lead to systematic variations in bit line resistance between groups of bit lines within a memory array. For example, in some cases, every fourth bit line of four neighboring (or adjacent) bit lines may be formed differently than the other three bit lines within a group of four neighboring bit lines. In one embodiment, bit line segment swapping may be used between blocks within a memory array in order to mitigate variations in bit line resistance. In another embodiment, each group of adjacent bit line segments may be offset (or staggered) per block such that the local routing necessary to connect bit line segments into bit lines may be simplified.
Abstract translation: 描述用于补偿非易失性存储器中位线电阻变化的方法。 在一些实施例中，使用多重图案化光刻来形成位线可能导致存储器阵列内的位线组之间的位线电阻的系统变化。 例如，在一些情况下，四个相邻（或相邻）位线的每第四位线可以与四个相邻位线组中的其它三个位线不同地形成。 在一个实施例中，可以在存储器阵列内的块之间使用位线段交换，以便减轻位线电阻的变化。 在另一个实施例中，每个相邻位线段的每个组可以每个块偏移（或交错），使得可以简化将位线段连接到位线所需的本地路由。
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公开(公告)号：US08988917B2
公开(公告)日：2015-03-24
申请号：US13755911
申请日：2013-01-31
Applicant: SanDisk Technologies, Inc.
Inventor： Kwang Ho Kim , Fumiaki Toyama , Seungpil Lee , Masaaki Higashitani
CPC classification number: G11C16/28
Abstract: Methods for compensating for variations in bit line resistance in non-volatile memories are described. In some embodiments, use of multiple patterning lithography for forming bit lines may lead to systematic variations in bit line resistance between groups of bit lines within a memory array. For example, in some cases, every fourth bit line of four neighboring (or adjacent) bit lines may be formed differently than the other three bit lines within a group of four neighboring bit lines. In one embodiment, bit line segment swapping may be used between blocks within a memory array in order to mitigate variations in bit line resistance. In another embodiment, each group of adjacent bit line segments may be offset (or staggered) per block such that the local routing necessary to connect bit line segments into bit lines may be simplified.
Abstract translation: 描述用于补偿非易失性存储器中位线电阻变化的方法。 在一些实施例中，使用多重图案化光刻来形成位线可能导致存储器阵列内的位线组之间的位线电阻的系统变化。 例如，在一些情况下，四个相邻（或相邻）位线的每第四位线可以与四个相邻位线组中的其它三个位线不同地形成。 在一个实施例中，可以在存储器阵列内的块之间使用位线段交换，以便减轻位线电阻的变化。 在另一个实施例中，每个相邻位线段的每个组可以每个块偏移（或交错），使得可以简化将位线段连接到位线所需的本地路由。
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公开(公告)号：US20140133229A1
公开(公告)日：2014-05-15
申请号：US13755894
申请日：2013-01-31
Applicant: SANDISK TECHNOLOGIES, INC.
Inventor： Teruhiko Kamei , Seungpil Lee , Siu Lung Chan , Kwang Ho Kim , Man Lung Mui
IPC: G11C16/28
CPC classification number: G11C16/0483 , G11C5/063 , G11C11/4097 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/28
Abstract: Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria. The sensing criteria may comprise a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a die or memory plane. Prior to performing a read or verify operation on a group of memory cells, a bit line read voltage used during sensing of the group of memory cells may be determined based on the plurality of bit line read voltages and a zone associated with the group of memory cells.
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公开(公告)号：US09047954B2
公开(公告)日：2015-06-02
申请号：US14256961
申请日：2014-04-19
Applicant: Sandisk Technologies, Inc.
Inventor： Teruhiko Kamei , Seungpil Lee , Siu Lung Chan , Kwang Ho Kim , Man Lung Mui
IPC: G11C5/06 , G11C16/04 , G11C16/28 , G11C11/4097 , G11C16/26
CPC classification number: G11C16/0483 , G11C5/063 , G11C11/4097 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/28
Abstract: Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria. The sensing criteria may comprise a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a die or memory plane. Prior to performing a read or verify operation on a group of memory cells, a bit line read voltage used during sensing of the group of memory cells may be determined based on the plurality of bit line read voltages and a zone associated with the group of memory cells.
Abstract translation: 描述了用于补偿存储器单元感测期间位线电阻变化的方法。 位线电阻的变化可能会在同一芯片上面对芯片或平面到平面。 在一些实施例中，对于管芯上的每个管芯或存储器平面，可以基于感测标准来确定与多个区域相关联的多个位线读取电压。 感测标准可以包括多个故障比特。 多个区域的每个区域可以与管芯或存储器平面内的存储器阵列区域相关联。 在对一组存储器单元执行读取或验证操作之前，可以基于多个位线读取电压和与该组存储器相关联的区域来确定在感测该组存储器单元期间使用的位线读取电压 细胞。
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公开(公告)号：US20140226405A1
公开(公告)日：2014-08-14
申请号：US14256961
申请日：2014-04-19
Applicant: SANDISK TECHNOLOGIES, INC.
Inventor： Teruhiko Kamei , Seungpil Lee , Siu Lung Chan , Kwang Ho Kim , Man Lung Mui
IPC: G11C16/28
CPC classification number: G11C16/0483 , G11C5/063 , G11C11/4097 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/28
Abstract: Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria. The sensing criteria may comprise a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a die or memory plane. Prior to performing a read or verify operation on a group of memory cells, a bit line read voltage used during sensing of the group of memory cells may be determined based on the plurality of bit line read voltages and a zone associated with the group of memory cells.
Abstract translation: 描述了用于补偿存储器单元感测期间位线电阻变化的方法。 位线电阻的变化可能会在同一芯片上面对芯片或平面到平面。 在一些实施例中，对于管芯上的每个管芯或存储器平面，可以基于感测标准来确定与多个区域相关联的多个位线读取电压。 感测标准可以包括多个故障比特。 多个区域的每个区域可以与管芯或存储器平面内的存储器阵列区域相关联。 在对一组存储器单元执行读取或验证操作之前，可以基于多个位线读取电压和与该组存储器相关联的区域来确定在感测该组存储器单元期间使用的位线读取电压 细胞。
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