公开(公告)号：US09818759B2

公开(公告)日：2017-11-14

申请号：US15268946

申请日：2016-09-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Jin Liu ,  Johann Alsmeier ,  Jixin Yu ,  Yoko Furihata ,  Hiroyuki Ogawa

IPC: H01L27/115 ,  H01L21/768 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L27/02 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0288 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

公开(公告)号：US20170179026A1

公开(公告)日：2017-06-22

申请号：US15269017

申请日：2016-09-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumiaki Toyama ,  Hiroyuki Ogawa ,  Yoko Furihata ,  James Kai ,  Yuki Mizutani ,  Jixin Yu ,  Jin Liu ,  Johann Alsmeier

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0288 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

公开(公告)号：US11043455B2

公开(公告)日：2021-06-22

申请号：US16519260

申请日：2019-07-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Johann Alsmeier ,  Jixin Yu

IPC: H01L23/535 ,  H01L27/11556 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11582

Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Memory stack structures are formed through the vertically alternating sequence. The vertically alternating sequence is divided into alternating stacks of insulating layers and sacrificial material layers by forming backside trenches therethrough. Each neighboring pair of alternating stacks is laterally spaced apart from each other by a respective backside trench. The sacrificial material layers are replaced with multipart layers. Each multipart layer includes a respective electrically conductive layer that laterally extends continuously between a respective neighboring pair of backside trenches and at least one dielectric material plate that is a remaining portion of a sacrificial material layer, is laterally enclosed by the respective electrically conductive layer, and is laterally spaced from a most proximal one of the backside trenches by a uniform lateral offset distance.

公开(公告)号：US10825826B2

公开(公告)日：2020-11-03

申请号：US16889030

申请日：2020-06-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Tae-Kyung Kim ,  Johann Alsmeier ,  Yan Li ,  Jian Chen

IPC: H01L27/11578 ,  G11C5/06 ,  G11C5/02

Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

公开(公告)号：US10804197B1

公开(公告)日：2020-10-13

申请号：US16516726

申请日：2019-07-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Motoki Kawasaki ,  Arata Okuyama ,  Xun Gu ,  Kengo Kajiwara ,  Jixin Yu

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11556

Abstract: A three-dimensional memory device includes a pair of alternating stacks of insulating layers and electrically conductive layers located over a semiconductor region, and laterally spaced from each other by a backside trench, memory stack structures extending through the pair of alternating, each memory stack structure containing a vertical semiconductor channel and a memory film, and a backside contact assembly located in the backside trench. The backside contact assembly includes an isolation dielectric spacer contacting the pair of alternating stacks, a conductive liner contacting inner sidewalls of the isolation dielectric spacer and a top surface of the semiconductor region, and composite non-metallic core containing at least one outer dielectric fill material portion that is laterally enclosed by a lower portion of the conductive liner and a dielectric core contacting an inner sidewall of the at least one outer dielectric fill material portion.

公开(公告)号：US10658381B1

公开(公告)日：2020-05-19

申请号：US16367455

申请日：2019-03-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Fumiaki Toyama ,  Masaaki Higashitani ,  Tong Zhang ,  Chun Ge ,  Xin Yuan Li ,  Johann Alsmeier

IPC: H01L27/11565 ,  H01L27/11582 ,  G11C5/06 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11558 ,  H01L27/11573

Abstract: Memory dies on a wafer may include multiple memory blocks including bit lines extending along different directions. A memory die may include a first-type plane including first memory blocks and a second-type plane including second memory blocks. In this case, memory blocks having different bit line directions may be formed within a same memory die. An exposure field may include multiple types of memory dies that are oriented in different orientations. The bit line directions may be oriented differently in the multiple types of memory dies. Each lithographic exposure process may include a first step in which lithographic patterns in first exposure fields are oriented in one direction, and a second step in which lithographic patterns in second exposure fields are oriented in another direction. The different orientations of bit lines and word lines may change local directions of stress to reduce wafer distortion.

公开(公告)号：US10381443B2

公开(公告)日：2019-08-13

申请号：US15976442

申请日：2018-05-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuyo Matsumoto ,  Yasuo Kasagi ,  Satoshi Shimizu ,  Hiroyuki Ogawa ,  Yohei Masamori ,  Jixin Yu ,  Tong Zhang ,  James Kai

IPC: H01L29/10 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.

公开(公告)号：US20190214344A1

公开(公告)日：2019-07-11

申请号：US15863205

申请日：2018-01-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Daxin Mao ,  Hiroyuki Ogawa ,  Johann Alsmeier

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L29/04 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/3105

CPC classification number: H01L23/535 ,  H01L21/31053 ,  H01L21/76846 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53266 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/04

Abstract: A contact level silicon oxide layer and a silicon nitride layer is formed over a semiconductor device on a semiconductor substrate. A contact via cavity extending to the semiconductor device is formed. A lower contact via structure portion is formed and recessed between top and bottom surface of the silicon nitride layer. An upper contact via structure portion including a hydrogen diffusion barrier material is formed in a remaining volume of the contact via cavity to provide a contact via structure. A three-dimensional memory array is formed over the silicon nitride layer. Metal interconnect structures are formed to provide electrical connection between the contact via structure and a node of the three-dimensional memory array. The hydrogen diffusion barrier material and the silicon nitride layer block downward diffusion of hydrogen.

公开(公告)号：US10074666B2

公开(公告)日：2018-09-11

申请号：US15401426

申请日：2017-01-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chun Ge ,  Yanli Zhang ,  Johann Alsmeier ,  Fabo Yu ,  Jixin Yu

IPC: H01L29/788 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: After formation of an alternating stack of insulating layers and sacrificial material layers, a memory opening can be formed through the alternating stack, which is subsequently filled with a columnar semiconductor pedestal portion and a memory stack structure. Breakage of the columnar semiconductor pedestal portion under mechanical stress can be avoided by growing a laterally protruding semiconductor portion by selective deposition of a semiconductor material after removal of the sacrificial material layers to form backside recesses. At least an outer portion of the laterally protruding semiconductor portion can be oxidized to form a tubular semiconductor oxide spacer. Electrically conductive layers can be formed in the backside recesses to provide word lines for a three-dimensional memory device.

公开(公告)号：US10038006B2

公开(公告)日：2018-07-31

申请号：US15269294

申请日：2016-09-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoko Furihata ,  Jixin Yu ,  Hiroyuki Ogawa ,  James Kai ,  Jin Liu ,  Johann Alsmeier

IPC: H01L29/76 ,  H01L29/792 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11565 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/02

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0288 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.