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    ULTRALOW POWER INFERENCE ENGINE WITH EXTERNAL MAGNETIC FIELD PROGRAMMING ASSISTANCE
    21.
    发明申请
    ULTRALOW POWER INFERENCE ENGINE WITH EXTERNAL MAGNETIC FIELD PROGRAMMING ASSISTANCE 有权

    公开(公告)号：US20220108158A1

    公开(公告)日：2022-04-07

    申请号：US17061798

    申请日：2020-10-02

    Applicant: SanDisk Technologies LLC

    Inventor： Michael Grobis ,  Michael Nicolas Albert Tran

    IPC: G06N3/063 ,  G06N3/08 ,  G11C11/15 ,  H03M1/66 ,  H03M1/12 ,  G06F17/16

    Abstract: An MRAM-based vector multiplication device, such as can be used for inferencing in a neural network, is presented that is ultralow power, low cost, and does not require special on-chip programming. A crosspoint array has an MRAM cell at each crosspoint junction and periphery array circuitry capable of supplying independent input voltages to each word line and reading current on each bit line. Vector multiplication is performed as an in-array multiplication of a vector of input voltages with matrix weight values encoded by the MRAM cell states. The MRAM cells can be individually programmed using a combination of input voltages and an external magnetic field. The external magnetic field is chosen so that a write voltage of one polarity reduces the anisotropy sufficiently to align the cell state with the external field, but is insufficient to align the cell if only half of the write voltage is applied.

    Concurrent multi-bit self-referenced read of programmable resistance memory cells in cross-point array
    22.
    发明授权
    Concurrent multi-bit self-referenced read of programmable resistance memory cells in cross-point array 有权

    公开(公告)号：US12237010B2

    公开(公告)日：2025-02-25

    申请号：US17939826

    申请日：2022-09-07

    Applicant: SanDisk Technologies LLC

    Inventor： Nathan Franklin ,  Ward Parkinson ,  Michael Grobis ,  James O'Toole

    IPC: G11C11/56 ,  G11C11/16 ,  H01L23/00 ,  H01L25/065 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

    Abstract: Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.

    Ultralow power inference engine with external magnetic field programming assistance
    23.
    发明授权
    Ultralow power inference engine with external magnetic field programming assistance 有权

    公开(公告)号：US12093812B2

    公开(公告)日：2024-09-17

    申请号：US17061798

    申请日：2020-10-02

    Applicant: SanDisk Technologies LLC

    Inventor： Michael Grobis ,  Michael Nicolas Albert Tran

    IPC: G11C11/15 ,  G06F17/16 ,  G06N3/065 ,  G06N3/08 ,  H03M1/12 ,  H03M1/66

    CPC classification number: G06N3/065 ,  G06F17/16 ,  G06N3/08 ,  G11C11/15 ,  H03M1/1205 ,  H03M1/662

    Abstract: An MRAM-based vector multiplication device, such as can be used for inferencing in a neural network, is presented that is ultralow power, low cost, and does not require special on-chip programming. A crosspoint array has an MRAM cell at each crosspoint junction and periphery array circuitry capable of supplying independent input voltages to each word line and reading current on each bit line. Vector multiplication is performed as an in-array multiplication of a vector of input voltages with matrix weight values encoded by the MRAM cell states. The MRAM cells can be individually programmed using a combination of input voltages and an external magnetic field. The external magnetic field is chosen so that a write voltage of one polarity reduces the anisotropy sufficiently to align the cell state with the external field, but is insufficient to align the cell if only half of the write voltage is applied.

    FAST SELF-REFERENCED READ OF PROGRAMMABLE RESISTANCE MEMORY CELLS
    24.
    发明公开
    FAST SELF-REFERENCED READ OF PROGRAMMABLE RESISTANCE MEMORY CELLS 审中-公开

    公开(公告)号：US20240184478A1

    公开(公告)日：2024-06-06

    申请号：US18356814

    申请日：2023-07-21

    Applicant: SanDisk Technologies LLC

    Inventor： Dimitri Houssameddine ,  Michael Nicolas Albert Tran ,  Ward Parkinson ,  Michael Grobis

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0619 ,  G06F3/0673

    Abstract: Technology is disclosed herein for reading programmable resistance memory cells. A first (faster) self-referenced read (SRR) of a group of memory cells is performed and if successful the read is complete. However, if the first SRR fails then a second (slower or nominal) SRR is performed. The bit error rate (BER) of the second SRR may be significantly lower than the BER of the first SRR. However, the BER of the first SRR may be low enough such that most of the time the first SRR is successful. Therefore, most of the time the read is completed with just the first SRR, thereby providing for an SRR having on average is faster than if just the second SRR had been used. Moreover, the effective BER of the SRR is extremely low due to the low BER of the second SRR.

    Concurrent multi-bit access in cross-point array
    26.
    发明授权
    Concurrent multi-bit access in cross-point array 有权

    公开(公告)号：US11488662B2

    公开(公告)日：2022-11-01

    申请号：US17099030

    申请日：2020-11-16

    Applicant: SanDisk Technologies LLC

    Inventor： Nathan Franklin ,  Ward Parkinson ,  Michael Grobis ,  James O'Toole

    IPC: G11C11/56 ,  G11C11/16 ,  H01L23/00 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L25/065

    Abstract: Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.

    Multi-level ultra-low power inference engine accelerator
    27.
    发明授权
    Multi-level ultra-low power inference engine accelerator 有权

    公开(公告)号：US11289171B1

    公开(公告)日：2022-03-29

    申请号：US17061820

    申请日：2020-10-02

    Applicant: SanDisk Technologies LLC

    Inventor： Michael Nicolas Albert Tran ,  Michael Grobis

    IPC: G11C17/16 ,  G11C17/18 ,  G06N3/08 ,  G11C11/54

    Abstract: Non-volatile memory structures for performing compute-in-memory inferencing for neural networks are presented. A memory array is formed according to a crosspoint architecture with a memory cell at each crosspoint junction. The multi-levels memory cells (MLCs) are formed of multiple of ultra-thin dielectric layers separated by metallic layers, where programming of the memory cell is done by selectively breaking down one or more of the dielectric layers by selecting the write voltage level. In an alternate set of embodiments, the memory cells are formed as anti-fuses.

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