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    Method on Forming an Isolation Film or a Semiconductor Device
    21.
    发明申请
    Method on Forming an Isolation Film or a Semiconductor Device 审中-公开
    形成绝缘膜或半导体器件的方法

    公开(公告)号：US20080242046A1

    公开(公告)日：2008-10-02

    申请号：US12112679

    申请日：2008-04-30

    申请人： Pil Geun Song ,  Young Jun Kim ,  Sang Wook Park

    发明人： Pil Geun Song ,  Young Jun Kim ,  Sang Wook Park

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76224

    摘要： A method of forming an isolation film in a semiconductor device is disclosed. The disclosed method includes performing a patterning process on a predetermined region of a semiconductor substrate in which a patterned pad film is formed, forming a trench defining an inactive region and an active region, forming a liner film on the entire surface including the trench, forming an insulating film for trench burial only within the trench, stripping the remaining liner film formed except for the inside of the trench and the patterned pad film formed below the liner film, forming a sacrificial film on the entire surface, and performing a polishing process on the entire surface in which the sacrificial film is formed until the semiconductor substrate of the active region is exposed, thereby forming the isolation film having no topology difference with the semiconductor substrate of the active region.

    摘要翻译： 公开了一种在半导体器件中形成隔离膜的方法。 所公开的方法包括在其上形成图案化焊盘膜的半导体衬底的预定区域上执行图案化工艺，形成限定非活性区域和有源区域的沟槽，在包括沟槽的整个表面上形成衬垫膜，形成 用于仅在沟槽内进行沟槽埋置的绝缘膜，剥离除了沟槽内部形成的剩余衬垫膜和形成在衬垫膜下方的图案化衬垫膜，在整个表面上形成牺牲膜，并对 其中形成牺牲膜的整个表面直到有源区的半导体衬底被暴露，从而形成与有源区的半导体衬底没有拓扑结构差异的隔离膜。

    Method of Forming an Isolation Film in a Semiconductor Device
    22.
    发明申请
    Method of Forming an Isolation Film in a Semiconductor Device 审中-公开
    在半导体器件中形成绝缘膜的方法

    公开(公告)号：US20080206955A1

    公开(公告)日：2008-08-28

    申请号：US12112725

    申请日：2008-04-30

    申请人： Pil Geun Song ,  Young Jun Kim ,  Sang Wook Park

    发明人： Pil Geun Song ,  Young Jun Kim ,  Sang Wook Park

    IPC分类号： H01L21/762 ,  H01L21/306

    CPC分类号： H01L21/76224

    摘要： A method of forming an isolation film in a semiconductor device is disclosed. The disclosed method includes performing a patterning process on a predetermined region of a semiconductor substrate in which a patterned pad film is formed, forming a trench defining an inactive region and an active region, forming a liner film on the entire surface including the trench, forming an insulating film for trench burial only within the trench, stripping the remaining liner film formed except for the inside of the trench and the patterned pad film formed below the liner film, forming a sacrificial film on the entire surface, and performing a polishing process on the entire surface in which the sacrificial film is formed until the semiconductor substrate of the active region is exposed, thereby forming the isolation film having no topology difference with the semiconductor substrate of the active region.

    摘要翻译： 公开了一种在半导体器件中形成隔离膜的方法。 所公开的方法包括在其上形成图案化焊盘膜的半导体衬底的预定区域上执行图案化工艺，形成限定非活性区域和有源区域的沟槽，在包括沟槽的整个表面上形成衬垫膜，形成 用于仅在沟槽内进行沟槽埋置的绝缘膜，剥离除了沟槽内部形成的剩余衬垫膜和形成在衬垫膜下方的图案化衬垫膜，在整个表面上形成牺牲膜，并对 其中形成牺牲膜的整个表面直到有源区的半导体衬底被暴露，从而形成与有源区的半导体衬底没有拓扑结构差异的隔离膜。

    Method of manufacturing a flash memory device
    23.
    发明授权
    Method of manufacturing a flash memory device 失效
    制造闪存装置的方法

    公开(公告)号：US07282420B2

    公开(公告)日：2007-10-16

    申请号：US11301866

    申请日：2005-12-13

    申请人： Kyoung Sik Han ,  Sang Wook Park ,  Sang Deok Kim

    发明人： Kyoung Sik Han ,  Sang Wook Park ,  Sang Deok Kim

    IPC分类号： H01L21/20

    CPC分类号： G11C16/3427 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524

    摘要： A method of manufacturing a flash memory device wherein a stacked structure of an oxide and nitride or the reverse is applied to insulation spacers provided on sidewalls of gates for forming source/drain regions. After completing the source/drain regions, spacers are formed on sidewalls of the gates by using an oxide film as a contacting buffer, thus minimizing the interference between gates and reducing the stress to cells, overcoming the disturbance of threshold voltage.

    摘要翻译： 一种制造闪速存储器件的方法，其中将氧化物和氮化物的叠层结构施加到设置在用于形成源极/漏极区域的栅极的侧壁上的绝缘隔板。 在完成源极/漏极区域之后，通过使用氧化膜作为接触缓冲器，在栅极的侧壁上形成间隔物，从而最小化栅极之间的干扰并减小对电池的应力，克服阈值电压的干扰。

    Method for forming isolation layer in semiconductor memory device
    24.
    发明授权
    Method for forming isolation layer in semiconductor memory device 失效
    在半导体存储器件中形成隔离层的方法

    公开(公告)号：US07259078B2

    公开(公告)日：2007-08-21

    申请号：US11016437

    申请日：2004-12-17

    申请人： Seung Cheol Lee ,  Sang Wook Park ,  Pil Geun Song

    发明人： Seung Cheol Lee ,  Sang Wook Park ,  Pil Geun Song

    IPC分类号： H01L21/76

    CPC分类号： H01L27/11526 ,  H01L21/76224 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11546

    摘要： Disclosed herein is a method for forming an isolation film of a semiconductor memory device. According to the disclosure, in a pre-treatment cleaning process performed before a tunnel oxide film is formed, a SC-1 cleaning process is performed at a temperature ranging from 60° C. to 70° C. Therefore, oxide films in a cell region and a peripheral region are recessed even in the SC-1 cleaning process as well as a DHF cleaning process. A DHF cleaning time can be thus reduced. Accordingly, the method can minimize loss of a silicon substrate by DHF and can thus control the depth of a moat.

    摘要翻译： 本文公开了一种用于形成半导体存储器件的隔离膜的方法。 根据公开内容，在形成隧道氧化膜之前进行的预处理清洗处理中，在60℃〜70℃的温度范围内进行SC-1清洗工序。因此，电池中的氧化膜 区域和外围区域即使在SC-1清洁处理以及DHF清洁过程中也是凹陷的。 因此可以减少DHF清洗时间。 因此，该方法可以通过DHF使硅衬底的损耗最小化，从而可以控制护城河的深度。

    Method of manufacturing flash memory device
    25.
    发明授权
    Method of manufacturing flash memory device 有权
    制造闪存设备的方法

    公开(公告)号：US07211484B2

    公开(公告)日：2007-05-01

    申请号：US10745008

    申请日：2003-12-23

    申请人： Seung Cheol Lee ,  Sang Wook Park

    发明人： Seung Cheol Lee ,  Sang Wook Park

    IPC分类号： H01L21/336 ,  H01L21/8242 ,  C09K13/00

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

    摘要： Disclosed is a method of manufacturing a flash memory device. In a flash memory device using a SA-STI scheme, a trench for isolation is buried with oxide. A field oxide film is then formed by means of a polishing process. Next, field oxide films of a cell region and a low-voltage transistor region are selectively etched by a given thickness. As EFH values of the cell region, the low-voltage transistor region and the high-voltage transistor region become same or similar, it is possible to secure stability of a subsequent process.

    摘要翻译： 公开了一种制造闪速存储器件的方法。 在使用SA-STI方案的闪存器件中，用氧化物掩埋用于隔离的沟槽。 然后通过抛光工艺形成场氧化膜。 接下来，选择性地蚀刻单元区域和低电压晶体管区域的场氧化膜一定厚度。 作为单元区域的EFH值，低电压晶体管区域和高压晶体管区域变得相同或相似，可以确保后续处理的稳定性。

    Method of manufacturing semiconductor device
    26.
    发明授权
    Method of manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US07192883B2

    公开(公告)日：2007-03-20

    申请号：US11009712

    申请日：2004-12-13

    申请人： Tae Jung Lim ,  Sang Wook Park

    发明人： Tae Jung Lim ,  Sang Wook Park

    IPC分类号： H01L21/461 ,  H01L21/302

    CPC分类号： H01L21/32139 ,  H01L21/3081 ,  H01L21/31111

    摘要： The present invention relates to a method of manufacturing a semiconductor device. A minute pattern is formed using a hard mask film of a series of a nitride film as an etch mask. Before a hard mask film removal process is performed, the step of performing given etching using an oxide film etchant is added to remove an abnormal oxide film on the nitride film. It is thus possible to effectively remove the hard mask film. Generation of voids in a pattern below the hard mask film can be also effectively prevented using BOE in which the composition ratio of HF and NH4F and an etching temperature are optimized as an oxide film etchant.

    摘要翻译： 本发明涉及半导体器件的制造方法。 使用一系列氮化物膜的硬掩模膜作为蚀刻掩模形成微小图案。 在进行硬掩膜剥离处理之前，添加使用氧化膜蚀刻剂进行给定蚀刻的步骤以去除氮化膜上的异常氧化膜。 因此，能够有效地除去硬掩模膜。 使用其中HF和NH 4 F的组成比和蚀刻温度作为氧化物膜蚀刻剂优化的BOE也可以有效地防止在硬掩模膜下方形成图案中的空隙。

    Method of manufacturing a semiconductor device
    30.
    发明授权
    Method of manufacturing a semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US06458693B1

    公开(公告)日：2002-10-01

    申请号：US09328694

    申请日：1999-06-09

    申请人： Sang Wook Park ,  Min Sik Jang

    发明人： Sang Wook Park ,  Min Sik Jang

    IPC分类号： H01L2144

    CPC分类号： H01L21/76886

    摘要： A semiconductor device which can reduce contact resistance, is disclosed. A semiconductor device according to the present invention includes a lower conductor pattern and an upper conductor pattern. The lower conductor pattern is in contact with the upper conductor pattern. The lower conductor pattern includes a first doped polysilicon layer, a first tungsten silicide layer and a cap layer formed sequentially. Here, the cap layer is formed to a doped polysilicon layer containing a small amount of tungsten and has stoichiometrical equivalent ratio x of Si higher than the first tungsten silicide layer. The upper conductor pattern includes a second doped polysilicon layer and a second tungsten layer formed sequentially. The contact of lower conductor pattern and the upper conductor pattern is substantially formed between the cap layer and the second doped polysilicon layer. Preferably, stoichiometrical equivalent ratio x of Si for the first tungsten silicide layer is 2.3 to 2.5 and stoichiometrical equivalent ratio x of Si for the cap layer is 2.6 to 2.9.

    摘要翻译： 公开了能够降低接触电阻的半导体装置。 根据本发明的半导体器件包括下导体图案和上导体图案。 下导体图案与上导体图案接触。 下导体图案包括依次形成的第一掺杂多晶硅层，第一硅化钨层和盖层。 这里，盖层形成为含有少量钨的掺杂多晶硅层，并且具有高于第一硅化钨层的Si的化学计量当量比x。 上导体图案包括顺序形成的第二掺杂多晶硅层和第二钨层。 下导体图案和上导体图案的接触基本形成在盖层和第二掺杂多晶硅层之间。 优选地，第一硅化钨层的Si的化学计量当量比x为2.3至2.5，并且用于盖层的Si的化学计量当量比x为2.6至2.9。