公开(公告)号：US08650414B2

公开(公告)日：2014-02-11

申请号：US12890222

申请日：2010-09-24

Applicant: Sarathy Jayakumar ,  Gopal R. Mundada ,  Palsamy Sakthikumar

Inventor： Sarathy Jayakumar ,  Gopal R. Mundada ,  Palsamy Sakthikumar

IPC: G06F1/00 ,  G06F13/00 ,  G06F3/00 ,  G06F11/00

CPC classification number: G06F11/3062 ,  G06F11/3031 ,  G06F11/3037 ,  G06F11/327

Abstract: Memory reconfiguration during system run-time is described. In one example, a system includes a memory slot to carry a memory board and to connect the memory board to a memory controller for read and write operations, a logic device having a plurality of status registers to record the status of the memory slot and a plurality of control registers to control the operation of the memory slot, and a bus interface coupled through direct signal lines to the memory slot to communicate status and control signals with the memory slot and coupled through a serial bus to the logic device to communicate status and control signals with the logic device.

Abstract translation: 描述系统运行时的内存重新配置。 在一个示例中，系统包括用于承载存储器板并且将存储器板连接到存储器控制器用于读取和写入操作的存储器插槽，具有多个状态寄存器以记录存储器槽的状态的逻辑设备和 多个控制寄存器来控制存储器插槽的操作，以及总线接口，通过直接信号线耦合到存储器插槽，以与存储器槽通信状态和控制信号，并通过串行总线耦合到逻辑器件以传送状态和 控制信号与逻辑器件。

公开(公告)号：US08448024B2

公开(公告)日：2013-05-21

申请号：US11804105

申请日：2007-05-16

Applicant: Mohan Kumar ,  Sarathy Jayakumar

Inventor： Mohan Kumar ,  Sarathy Jayakumar

IPC: G06F11/00

CPC classification number: G06F11/34 ,  G06F11/0706 ,  G06F11/0769

Abstract: A firmware assisted error handling scheme in a computer system has been disclosed. In one embodiment, firmware is used to access one or more hardware-specific error registers within the computer system in response to a system management interrupt (SMI) trap. Using the firmware, an error record in a common error record format is constructed. The error record is made available to an operating system (OS) within the computer system.

Abstract translation: 已经公开了计算机系统中的固件辅助错误处理方案。 在一个实施例中，响应于系统管理中断（SMI）陷阱，固件用于访问计算机系统内的一个或多个硬件特定的错误寄存器。 使用固件，构建一个常见错误记录格式的错误记录。 错误记录可用于计算机系统内的操作系统（OS）。

公开(公告)号：US20110179311A1

公开(公告)日：2011-07-21

申请号：US12971868

申请日：2010-12-17

Applicant: Murugasamy K. Nachimuthu ,  Mohan J. Kumar ,  Sarathy Jayakumar ,  Chung-Chi Wang

Inventor： Murugasamy K. Nachimuthu ,  Mohan J. Kumar ,  Sarathy Jayakumar ,  Chung-Chi Wang

IPC: G06F11/00

CPC classification number: G06F11/3676

Abstract: In some embodiments a request is received to perform an error injection or a memory migration, a mode is entered that blocks requests from agents other than a current processor core or thread, the error is injected or the memory is migrated, and the mode that blocks requests from the agents other than the current processor core or thread is exited. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，接收到执行错误注入或存储器迁移的请求，输入阻止来自除当前处理器核心或线程以外的代理的请求的模式，注入错误或存储器迁移的模式以及阻止 来自除当前处理器核心或线程之外的代理的请求退出。 描述和要求保护其他实施例。

公开(公告)号：US20150378841A1

公开(公告)日：2015-12-31

申请号：US14319361

申请日：2014-06-30

Applicant: Sarathy Jayakumar ,  Mohan J. Kumar ,  Adam J. Brooks ,  George Vergis

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Adam J. Brooks ,  George Vergis

IPC: G06F11/14 ,  G06F3/06 ,  G11C14/00 ,  G06F9/44

CPC classification number: G06F9/4401 ,  G06F11/1441 ,  G06F11/2015

Abstract: Examples may include communicating with a controller for a non-volatile dual in-line memory module through a system management bus (SMBus) interface. In some examples, selective assertion of bits maintained in registers accessible through the SMBus interface may enable communication with the controller. The selective assertion may be based on a register map.

Abstract translation: 示例可以包括通过系统管理总线（SMBus）接口与用于非易失性双列直插存储器模块的控制器进行通信。 在一些示例中，通过SMBus接口可访问的寄存器中保持的位的选择性断言可以实现与控制器的通信。 选择性断言可以基于寄存器映射。

公开(公告)号：US20140059368A1

公开(公告)日：2014-02-27

申请号：US13977635

申请日：2012-11-21

Applicant: Neelam Chandwani ,  Mohan Kumar ,  Sarathy Jayakumar

Inventor： Mohan Kumar ,  Sarathy Jayakumar ,  Neelam Chandwani

IPC: G06F1/32

CPC classification number: G06F9/4403 ,  G06F1/206 ,  G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/22 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/384 ,  G06F9/44 ,  G06F9/4401 ,  G06F9/4418 ,  G06F9/445 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3447 ,  G06F11/3466 ,  G06F11/3664 ,  G06F11/3672 ,  G06F11/3688 ,  G06F15/7871 ,  G06F17/30339 ,  G06F2209/501 ,  G06F2217/78 ,  Y02D10/126 ,  Y02D10/172

Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

Abstract translation: 在一些实施例中，只要平台硬件符合PPM接口，PPM接口可以被提供有功能，以便于一个或多个存储器节点的OS存储器功率状态管理，而不管特定的平台硬件配置。

公开(公告)号：US20140053024A1

公开(公告)日：2014-02-20

申请号：US13977625

申请日：2012-11-21

Applicant: Sarathy Jayakumar ,  Jose Andy Vargas ,  Mohan Kumar

Inventor： Mohan Kumar ,  Sarathy Jayakumar ,  Jose Andy Vargas

IPC: G06F11/36

CPC classification number: G06F9/4403 ,  G06F1/206 ,  G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/22 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/384 ,  G06F9/44 ,  G06F9/4401 ,  G06F9/4418 ,  G06F9/445 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3447 ,  G06F11/3466 ,  G06F11/3664 ,  G06F11/3672 ,  G06F11/3688 ,  G06F15/7871 ,  G06F17/30339 ,  G06F2209/501 ,  G06F2217/78 ,  Y02D10/126 ,  Y02D10/172

Abstract: In some embodiments, a PPM interface for a computing platform may be provided with functionality to facilitate, to an OS through the PPM interface, hardware component error injection.

Abstract translation: 在一些实施例中，可以提供用于计算平台的PPM接口，其具有通过PPM接口向OS提供硬件组件错误注入的功能。

公开(公告)号：US20130212426A1

公开(公告)日：2013-08-15

申请号：US13848830

申请日：2013-03-22

Applicant: Robert C. Swanson ,  Mahesh S. Natu ,  Rahul Khanna ,  Murugasamy K. Nachimuthu ,  Sarathy Jayakumar ,  Anil S. Keshavamurthy ,  Narayan Ranganathan

Inventor： Robert C. Swanson ,  Mahesh S. Natu ,  Rahul Khanna ,  Murugasamy K. Nachimuthu ,  Sarathy Jayakumar ,  Anil S. Keshavamurthy ,  Narayan Ranganathan

IPC: G06F11/20

CPC classification number: G06F11/203 ,  G06F11/1666 ,  G06F11/20

Abstract: In one embodiment, the present invention provides an ability to handle an error occurring during a memory migration operation in a high availability system. In addition, a method can be used to dynamically remap a memory page stored in a non-mirrored memory region of memory to a mirrored memory region. This dynamic remapping may be responsive to a determination that the memory page has been accessed more than a threshold number of times, indicating a criticality of information on the page. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明提供了处理在高可用性系统中的存储器迁移操作期间发生的错误的能力。 此外，可以使用一种方法来将存储在存储器的非镜像存储器区域中的存储器页面动态重映射到镜像存储器区域。 该动态重新映射可以响应于确定存储器页已经被访问多于阈值次数，指示页面上的信息的关键性。 描述和要求保护其他实施例。

公开(公告)号：US08407516B2

公开(公告)日：2013-03-26

申请号：US12645778

申请日：2009-12-23

Applicant: Robert C. Swanson ,  Mahesh S. Natu ,  Rahul Khanna ,  Murugasamy K. Nachimuthu ,  Sarathy Jayakumar ,  Anil S. Keshavamurthy ,  Narayan Ranganathan

Inventor： Robert C. Swanson ,  Mahesh S. Natu ,  Rahul Khanna ,  Murugasamy K. Nachimuthu ,  Sarathy Jayakumar ,  Anil S. Keshavamurthy ,  Narayan Ranganathan

IPC: G06F11/00

CPC classification number: G06F11/203 ,  G06F11/1666 ,  G06F11/20

Abstract: In one embodiment, the present invention provides an ability to handle an error occurring during a memory migration operation in a high availability system. In addition, a method can be used to dynamically remap a memory page stored in a non-mirrored memory region of memory to a mirrored memory region. This dynamic remapping may be responsive to a determination that the memory page has been accessed more than a threshold number of times, indicating a criticality of information on the page. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明提供了处理在高可用性系统中的存储器迁移操作期间发生的错误的能力。 此外，可以使用一种方法来将存储在存储器的非镜像存储器区域中的存储器页面动态重映射到镜像存储器区域。 该动态重新映射可以响应于确定存储器页已经被访问多于阈值次数，指示页面上的信息的关键性。 描述和要求保护其他实施例。

公开(公告)号：US20100332707A1

公开(公告)日：2010-12-30

申请号：US12459423

申请日：2009-06-30

Applicant: Sarathy Jayakumar

Inventor： Sarathy Jayakumar

IPC: G06F13/00

CPC classification number: G06F9/4411

Abstract: In some embodiments a signal is sent from a Basic Input/Output System to a device to indicate that the Basic Input/Output System needs to obtain control of shared resources. A signal is sent from the device to the Basic Input/Output System that indicates that the Basic Input/Output System can now control the shared resources. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，信号从基本输入/输出系统发送到设备，以指示基本输入/输出系统需要获得对共享资源的控制。 信号从设备发送到基本输入/输出系统，指示基本输入/输出系统现在可以控制共享资源。 描述和要求保护其他实施例。

公开(公告)号：US07725637B2

公开(公告)日：2010-05-25

申请号：US11967299

申请日：2007-12-31

Applicant: Mohan Kumar ,  Sarathy Jayakumar ,  Sham M Datta

Inventor： Mohan Kumar ,  Sarathy Jayakumar ,  Sham M Datta

IPC: G06F13/24

CPC classification number: G06F9/4812

Abstract: A method includes determining a plurality of memory addresses, each memory address being different from one another. The method further includes generating a plurality of system management interrupt interprocessor interrupts, each system management interrupt interprocessor interrupt having a corresponding processor in a plurality of processors in a system and each system management interrupt interprocessor interrupt including one of the plurality of memory addresses. The method further includes directing each system management interrupt interprocessor interrupt to the corresponding processor. An associated machine readable medium is also disclosed.

Abstract translation: 一种方法包括确定多个存储器地址，每个存储器地址彼此不同。 该方法还包括产生多个系统管理中断处理器中断，每个系统管理中断处理器中断在系统中的多个处理器中具有对应的处理器，并且每个系统管理中断处理器中断包括多个存储器地址之一。 该方法还包括将每个系统管理中断处理器中断引导到相应的处理器。 还公开了一种相关的机器可读介质。