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公开(公告)号：US10255931B1
公开(公告)日：2019-04-09
申请号：US15912480
申请日：2018-03-05
Applicant: Seagate Technology LLC
Inventor： Jason Charles Jury , Marcus Marrow , Michael J Link , Jason Bellorado
Abstract: An apparatus may include a circuit configured to generate a set of first ADC samples based on a first signal associated with a first read head position and a failed segment and to generate a set of second ADC samples based on a second signal associated with a second read head position and the failed segment. The circuit may then generate, by a MISO equalizer, a set of equalized ADC samples based on the set of first ADC samples and the set of second ADC samples.
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公开(公告)号：US10177771B1
公开(公告)日：2019-01-08
申请号：US15724001
申请日：2017-10-03
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
Abstract: An apparatus may include a circuit configured to receive first and second samples of an underlying data from respective first and second sample periods and which correspond to respective first and second sensors, a phase control value may have first and second values during respective first and second sample periods. The phase control value may be a control value for a sample clock signal. The circuit may also determine a difference in the phase control value between the first value and the second value. The circuit may then digitally interpolate the first and second samples to produce a phase shifted first and second samples where the digital interpolation of at least one of the first and second samples mat be at least in part based on the difference in the phase control value to compensate for a phase misalignment between the first sample and the second sample.
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公开(公告)号：US10152457B1
公开(公告)日：2018-12-11
申请号：US15334167
申请日：2016-10-25
Applicant: Seagate Technology LLC
Inventor： Jason Vincent Bellorado , Marcus Marrow , Zheng Wu
Abstract: An apparatus may include a circuit including a filter configured to update one or more adaptive coefficients of the filter based on an error signal. Further, the circuit may update a constrained coefficient of the filter based on the one or more adaptive coefficients, the constrained coefficient and a desired value. Moreover, the circuit may generate a sample of a sample sequence based on the one or more adaptive coefficients and the updated constrained coefficient, the error signal being based on the sample sequence.
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公开(公告)号：US09998136B1
公开(公告)日：2018-06-12
申请号：US15436709
申请日：2017-02-17
Applicant: Seagate Technology LLC
Inventor： Zheng Wu , Jason Vincent Bellorado , Marcus Marrow
CPC classification number: H03M1/18 , G11B20/10027 , G11B20/10037 , G11B20/10222 , H03M1/12 , H03M1/124
Abstract: An apparatus may include a circuit configured to generate, by an analog to digital converter (ADC), one or more ADC samples based on an input signal. The circuit may be further configured to generate a first estimated signal using a first channel pulse response estimation with a gain constraint based on the one or more ADC samples and generate a second estimated signal using a second channel pulse response estimation with a phase constraint based on the one or more ADC samples.
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公开(公告)号：US09954537B1
公开(公告)日：2018-04-24
申请号：US15390453
申请日：2016-12-23
Applicant: Seagate Technology LLC
Inventor： Marcus Marrow , Kenneth John Evans , Jason Vincent Bellorado
CPC classification number: H03L7/08 , G06F1/022 , H03K5/135 , H03L7/0814
Abstract: In certain embodiments, an apparatus may comprise a circuit configured to scale a phase control value from an external phase control resolution of an external clock frequency to an internal phase control resolution of an internal clock frequency to generate a target phase control value. The circuit may also determine a difference between a current phase control value and the target phase control value and determine a phase step value based on the difference. Further, the circuit may modify a current phase control value based on the phase step value and generate a phase controlled clock signal at the internal clock frequency using the modified phase control value. Additionally, the circuit may divide the phase controlled clock signal at the internal clock frequency to generate a phase controlled clock signal at the external clock frequency.
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Patent Agency Ranking
公开(公告)号：US11675533B2
公开(公告)日：2023-06-13
申请号：US17825905
申请日：2022-05-26
Applicant: Seagate Technology LLC
Inventor： Zheng Wang , Marcus Marrow , Jason Bellorado
CPC classification number: G06F3/0656 , G06F3/0604 , G06F3/0673 , G06F18/295 , H03M13/3961 , H03M13/45
Abstract: A one-shot state transition decoder receives a codeword having N-bits. The decoder reads a first D-bits of the codeword to determine a stitching location d within the codeword. The stitching location identifies a start bit of unencoded data in the codeword. The codeword is decoded into an output buffer for user data of L bits, where N>L. Parameters of the decoder are set before the decoding, including setting a length of the codeword to N−L+d and a number of expected decoded bits to d. The decoding including decoding the d bits based on a set of state transition probabilities and copying decoded bits into the output buffer, the unencoded data being copied to the end of the output buffer.
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公开(公告)号：US11170815B1
公开(公告)日：2021-11-09
申请号：US16986590
申请日：2020-08-06
Applicant: Seagate Technology LLC
Inventor： Zheng Wu , Jason Bellorado , Marcus Marrow , Vincent Brendan Ashe
Abstract: An apparatus may comprise a circuit configured to receive first underlying data corresponding to a first signal and receive a second signal corresponding to second underlying data. The circuit may determine an interference component signal based on the first underlying data corresponding to the first signal and a first channel pulse response shape for the first signal, determine estimated decisions corresponding to the second signal based on the second signal, and determine an estimated signal based on the estimated decisions corresponding to the second signal and a second channel pulse response shape for the second signal. The circuit may then generate a remaining signal based on the estimated signal and the second signal, generate an error signal based on the interference component signal and the remaining signal, and adapt one or more parameters of the first channel pulse response shape based on the error signal.
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公开(公告)号：US11016681B1
公开(公告)日：2021-05-25
申请号：US16051244
申请日：2018-07-31
Applicant: Seagate Technology LLC
Inventor： Marcus Marrow , Jason Bellorado , Vincent Brendan Ashe , Zheng Wu
Abstract: An apparatus may include a circuit configured to receive an input signal at an input and process the input signal using a set of channel parameters. The circuit may further determine an error metric for the processing of the input signal using the set of channel parameters, compare the error metric to a plurality of thresholds, and when the error metric matches one of the plurality of thresholds, adapt, using an adaptation algorithm, the set of channel parameters to produce an updated set of channel parameters for use by the circuit as the set of channel parameters in subsequent processing of the input signal, the adaptation of the set of channel parameters being based on a weight corresponding to the matching threshold of the plurality of thresholds.
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公开(公告)号：US10522177B1
公开(公告)日：2019-12-31
申请号：US16051234
申请日：2018-07-31
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow
Abstract: Systems and methods are disclosed for timing servo operations within a channel based on a counter for a disc locked clock. In certain embodiments, an apparatus may comprise a servo channel configured to lock a frequency of a servo channel clock to a rotational velocity of a disc data storage medium, and maintain a counter of clock cycles for the servo channel clock. The servo channel may perform operations to read servo data from a servo sector on the disc data storage medium at a first counter value selected relative to a target counter value corresponding to an expected location of a servo timing mark (STM).
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公开(公告)号：US10468060B1
公开(公告)日：2019-11-05
申请号：US16144659
申请日：2018-09-27
Applicant: Seagate Technology LLC
Inventor： Zheng Wu , Jason Bellorado , Marcus Marrow , Vincent Brendan Ashe
Abstract: An apparatus may comprise a circuit configured to receive first underlying data corresponding to a first signal and receive a second signal corresponding to second underlying data. The circuit may determine an interference component signal based on the first underlying data corresponding to the first signal and a first channel pulse response shape for the first signal, determine estimated decisions corresponding to the second signal based on the second signal, and determine an estimated signal based on the estimated decisions corresponding to the second signal and a second channel pulse response shape for the second signal. The circuit may then generate a remaining signal based on the estimated signal and the second signal, generate an error signal based on the interference component signal and the remaining signal, and adapt one or more parameters of the first channel pulse response shape based on the error signal.
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