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21.发明申请公开(公告)号：US20180061307A1
公开(公告)日：2018-03-01
申请号：US15684085
申请日：2017-08-23
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hiroki INOUE , Kei TAKAHASHI
CPC classification number: G09G3/2096 , G09G3/3275 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G5/026 , G09G2300/0408 , G09G2300/046 , G09G2300/0871 , G09G2310/0286 , G09G2310/0291 , G09G2320/0666 , G09G2330/06 , G09G2340/02 , G09G2360/121 , G09G2360/144 , G09G2360/18 , G09G2370/08 , G09G2370/14 , H01L27/1225 , H01L27/3211 , H01L27/3244 , H03F3/195 , H03F3/3022 , H03F3/45183 , H03F3/45192 , H03F3/45219 , H03F3/45475 , H03F3/68 , H03F2203/45652
Abstract: The transmission delay time of a receiver for receiving a differential signal is reduced. A first amplifier circuit is provided in an input stage of the receiver, and a second amplifier circuit is provided in an output stage of the receiver. The first amplifier circuit is a differential input, differential output amplifier circuit. The second amplifier circuit is a differential input, single-ended output amplifier circuit. A first power supply voltage and a second power supply voltage are input as a high-level power supply voltage and a low-level power supply voltage to the first amplifier circuit and the second amplifier circuit, respectively. The withstand voltage of transistors of a differential pair of the first amplifier circuit is higher than the withstand voltage of another transistor included in the first amplifier circuit and a transistor included in the second amplifier circuit.
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公开(公告)号：US20170263777A1
公开(公告)日：2017-09-14
申请号：US15609513
申请日：2017-05-31
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei YAMAZAKI , Jun KOYAMA , Hiroyuki MIYAKE , Kei TAKAHASHI , Kouhei TOYOTAKA , Masashi TSUBUKU , Kosei NODA , Hideaki KUWABARA
IPC: H01L29/786 , H01L23/552 , H01L23/66 , H01L49/02 , H01L27/02 , H01L27/108 , H01L27/12 , H01L21/84 , H01L25/16
CPC classification number: H01L29/7869 , H01L21/84 , H01L23/552 , H01L23/60 , H01L23/66 , H01L25/16 , H01L27/0222 , H01L27/10873 , H01L27/12 , H01L27/1225 , H01L28/20 , H01L28/60 , H01L29/78609 , H01L2223/6677 , H01L2924/0002 , H01L2924/00
Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit included in an LSI, a CPU, or a memory is manufactured using the transistor which is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor obtained by removal of impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than a silicon semiconductor, and is formed over a semiconductor substrate. With the transistor which is formed over the semiconductor substrate and includes the highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device whose power consumption due to leakage current is low can be realized.
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公开(公告)号：US20170063112A1
公开(公告)日：2017-03-02
申请号：US15238793
申请日：2016-08-17
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Kei TAKAHASHI
IPC: H02J7/00 , G09G3/3225 , G09G3/36
CPC classification number: H02J7/0026 , G09G3/3225 , G09G3/3648 , G09G3/3696 , G09G2300/0842 , G09G2330/021
Abstract: A battery-monitoring IC with small power consumption is provided. A power storage device includes a storage element and an IC. The IC monitors the electromotive force of the power storage element. The IC includes a bias circuit, a holding circuit, and an amplifier. The holding circuit includes a first transistor and a capacitor. The amplifier includes a second transistor. The bias circuit is electrically connected to a gate of the second transistor through the first transistor. A first terminal of the capacitor is electrically connected to the gate of the second transistor. A first transistor preferably includes an oxide semiconductor in a channel formation region.
Abstract translation: 提供功耗小的电池监控IC。 蓄电装置包括存储元件和IC。 IC监视蓄电元件的电动势。 IC包括偏置电路，保持电路和放大器。 保持电路包括第一晶体管和电容器。 放大器包括第二晶体管。 偏置电路通过第一晶体管电连接到第二晶体管的栅极。 电容器的第一端子电连接到第二晶体管的栅极。 第一晶体管优选地在沟道形成区域中包括氧化物半导体。
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公开(公告)号：US20170033792A1
公开(公告)日：2017-02-02
申请号：US15207631
申请日：2016-07-12
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Kei TAKAHASHI , Atsushi MIYAGUCHI
IPC: H03K17/687 , H01L29/786 , H01L27/12
CPC classification number: H01L29/78648 , G02F1/133345 , G02F1/133512 , G02F1/134309 , G02F1/136286 , G02F1/1368 , G02F2201/121 , G02F2201/123 , G06F3/041 , H01L27/1225 , H01L27/124 , H01L27/1251 , H01L29/7869 , H03K19/0021 , H03K2217/0036
Abstract: A semiconductor device with a novel structure is provided. A semiconductor device with reduced power consumption is provided. A circuit which is configured to supply a signal from an input terminal to both a gate and a backgate of a transistor in a first state and to only the gate in a second state is provided. With this structure, a current supply capability of the transistor can be changed between operations; accordingly, power consumption can be reduced by the amount needed to charge the backgate.
Abstract translation: 提供具有新颖结构的半导体器件。 提供了具有降低功耗的半导体器件。 提供了一种电路，其被配置为将信号从第一状态的晶体管的栅极和背栅极的输入端子提供给第二状态的栅极。 利用这种结构，可以在操作之间改变晶体管的电流供应能力; 因此，可以减少对后门充电所需的功率消耗。
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公开(公告)号：US20170012453A1
公开(公告)日：2017-01-12
申请号：US15274323
申请日：2016-09-23
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Junpei MOMO , Hiroyuki MIYAKE , Kei TAKAHASHI
IPC: H02J7/00 , H01M10/0525 , H01M10/42 , H01M10/46 , H01M10/44
Abstract: A decrease in the capacity of a power storage device is inhibited by adjusting or reducing imbalance in the amount of inserted and extracted carrier ions between positive and negative electrodes, which is caused by decomposition of an electrolyte solution of the negative electrode. Further, the capacity of the power storage device can be restored. Furthermore, impurities in the electrolyte solution can be decomposed with the use of the third electrode. A power storage device including positive and negative electrodes, an electrolyte, and a third electrode is provided. The third electrode has an adequate electrostatic capacitance. The third electrode can include a material with a large surface area. In addition, a method for charging the power storage device including the steps of performing charging by applying a current between the positive and negative electrodes, and performing additional applying a current between the third electrode and the negative electrode is provided.
Abstract translation: 通过调节或减少由负极的电解液的分解引起的正极和负极之间的插入和提取的载流子的量的不平衡，可以抑制蓄电装置的容量的减小。 此外，可以恢复蓄电装置的容量。 此外，电解质溶液中的杂质可以通过使用第三电极而分解。 提供了包括正极和负极，电解质和第三电极的蓄电装置。 第三电极具有足够的静电电容。 第三电极可以包括具有大表面积的材料。 另外，提供了一种蓄电装置的充电方法，包括以下步骤：通过在正极和负极之间施加电流并且在第三电极和负极之间执行附加的电流来进行充电。
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Patent Agency Ranking
公开(公告)号：US20160260839A1
公开(公告)日：2016-09-08
申请号：US15153119
申请日：2016-05-12
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei YAMAZAKI , Kei TAKAHASHI , Yoshiaki ITO
IPC: H01L29/786 , H01L29/66 , H01L29/24
CPC classification number: H01L29/7869 , H01L27/1251 , H01L29/045 , H01L29/0611 , H01L29/24 , H01L29/41733 , H01L29/42384 , H01L29/66477 , H01L29/66969 , H01L29/78618 , H01L29/78642 , H01L29/78648 , H01L29/78693 , H01L29/78696
Abstract: It is an object to provide a semiconductor device having a new productive semiconductor material and a new structure. The semiconductor device includes a first conductive layer over a substrate, a first insulating layer which covers the first conductive layer, an oxide semiconductor layer over the first insulating layer that overlaps with part of the first conductive layer and has a crystal region in a surface part, second and third conductive layers formed in contact with the oxide semiconductor layer, an insulating layer which covers the oxide semiconductor layer and the second and third conductive layers, and a fourth conductive layer over the insulating layer that overlaps with part of the oxide semiconductor layer.
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27.发明申请公开(公告)号：US20160071463A1
公开(公告)日：2016-03-10
申请号：US14837595
申请日：2015-08-27
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Kei TAKAHASHI , Hidetomo KOBAYASHI
IPC: G09G3/32 , H01L27/32 , H03K17/00 , H01L29/786
CPC classification number: G09G3/3275 , G09G3/3225 , G09G3/3291 , G09G2300/0842 , G09G2300/0861 , G09G2310/0262 , G09G2310/027 , G09G2310/0297 , G09G2320/0295 , H01L27/3262 , H01L27/3276 , H01L29/7869 , H03K17/007
Abstract: A semiconductor device including a test circuit is miniaturized. The semiconductor device includes r first input terminals (r is an integer of 2 or more), a second input terminal, r functional circuits, a demultiplexer, and a switch circuit. The demultiplexer is a pass transistor logic circuit. R output terminals of the demultiplexer are electrically connected to respective input terminals of the functional circuit and the input terminal is electrically connected to the second input teiminal. Input terminals of the r circuits are electrically connected to the respective first input terminals through the switch circuit. For example, a signal for verification is input to the first input terminal in verification of the functional circuit to operate the demultiplexer. One signal for verification is input to r functional circuits by the demultiplexer.
Abstract translation: 包括测试电路的半导体器件小型化。 半导体装置包括r个第一输入端子（r为2以上的整数），第二输入端子，r功能电路，解复用器和开关电路。 解复用器是传输晶体管逻辑电路。 解复用器的R个输出端子电连接到功能电路的各个输入端子，并且输入端子电连接到第二输入端子。 r电路的输入端子通过开关电路与各个第一输入端子电连接。 例如，在验证功能电路以操作解复用器时，将用于验证的信号输入到第一输入端。 用于验证的一个信号被解复用器输入到r个功能电路。
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公开(公告)号：US20150317028A1
公开(公告)日：2015-11-05
申请号：US14695737
申请日：2015-04-24
Applicant: Semiconductor Energy Laboratory Co., LTD.
Inventor： Kei TAKAHASHI , Hiroyuki MIYAKE
Abstract: A circuit which detects an output current from a pixel and an output current from an input device, and converts the output current into data is provided. The current detection circuit includes an integrator circuit, a comparator, a counter, and a latch. The integrator circuit integrates the potential of a first signal during a period determined by a second signal and outputting it as a third signal. The comparator compares the potential of the third signal with a first potential and outputting a fourth signal. The counter outputs the number of pulses included in a fifth signal as a sixth signal during a period determined by the fourth signal. The latch holds the sixth signal. The integrator circuit preferably further includes an operational amplifier and some capacitors. The first signal is supplied from a pixel included in a display device or an input portion included in an input device.
Abstract translation: 提供了检测来自像素的输出电流和来自输入装置的输出电流并将输出电流转换为数据的电路。 电流检测电路包括积分器电路，比较器，计数器和锁存器。 积分器电路在由第二信号确定的周期中积分第一信号的电位，并将其作为第三信号输出。 比较器将第三信号的电位与第一电位进行比较，并输出第四信号。 在由第四信号确定的周期期间，计数器输出包括在第五信号中的脉冲数作为第六信号。 锁存器保持第六个信号。 积分器电路优选地还包括运算放大器和一些电容器。 第一信号从包括在显示装置中的像素或包括在输入装置中的输入部分提供。
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公开(公告)号：US20140162402A1
公开(公告)日：2014-06-12
申请号：US14182726
申请日：2014-02-18
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei YAMAZAKI , Kei TAKAHASHI , Yoshiaki ITO
IPC: H01L29/66
CPC classification number: H01L29/7869 , H01L27/1251 , H01L29/045 , H01L29/0611 , H01L29/24 , H01L29/41733 , H01L29/42384 , H01L29/66477 , H01L29/66969 , H01L29/78618 , H01L29/78642 , H01L29/78648 , H01L29/78693 , H01L29/78696
Abstract: It is an object to provide a semiconductor device having a new productive semiconductor material and a new structure. The semiconductor device includes a first conductive layer over a substrate, a first insulating layer which covers the first conductive layer, an oxide semiconductor layer over the first insulating layer that overlaps with part of the first conductive layer and has a crystal region in a surface part, second and third conductive layers formed in contact with the oxide semiconductor layer, an insulating layer which covers the oxide semiconductor layer and the second and third conductive layers, and a fourth conductive layer over the insulating layer that overlaps with part of the oxide semiconductor layer.
Abstract translation: 本发明的目的是提供一种具有新的生产半导体材料和新结构的半导体器件。 半导体器件包括：衬底上的第一导电层，覆盖第一导电层的第一绝缘层，与第一导电层的一部分重叠的第一绝缘层上的氧化物半导体层，并且在表面部分中具有晶体区域 形成为与氧化物半导体层接触的第二和第三导电层，覆盖氧化物半导体层和第二和第三导电层的绝缘层，以及绝缘层上的与氧化物半导体层的一部分重叠的第四导电层 。
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公开(公告)号：US20250141355A1
公开(公告)日：2025-05-01
申请号：US18986896
申请日：2024-12-19
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hiroki INOUE , Kousuke SASAKI , Yuto YAKUBO , Kei TAKAHASHI
Abstract: A novel oscillator, an amplifier circuit, an inverter circuit, an amplifier circuit, a battery control circuit, a battery protection circuit, a power storage device, a semiconductor device, an electric device, and the like are provided. The semiconductor device includes an oscillator including a first transistor containing a metal oxide, and a second transistor to a fifth transistor, in which a first potential is supplied to a gate of the second transistor and a gate of the third transistor when the first transistor is turned on, and the first potential is held when the first transistor is turned off. The oscillator supplies a first signal based on the first potential to a first circuit. The first circuit performs at least one of shaping and amplification on the first signal. The second transistor and the fourth transistor are connected in series, and the third transistor and the fifth transistor are connected in series. A source or a drain of the third transistor is electrically connected to a gate of the fourth transistor, and a source or a drain of the fourth transistor is electrically connected to the gate of the third transistor.
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