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公开(公告)号：US20140225641A1
公开(公告)日：2014-08-14
申请号：US14170825
申请日：2014-02-03
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Munehiro Kozuma , Yoshiyuki Kurokawa , Takayuki Ikeda , Takeshi Aoki
IPC: H03K19/177
CPC classification number: H03K19/0013 , H01L27/1225 , H01L27/124 , H01L29/24 , H01L29/7869 , H03K19/09441 , H03K19/1737 , H03K19/17728 , H03K19/17748 , H03K19/1776
Abstract: A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor.
Abstract translation: 可编程逻辑器件包括多个可编程逻辑元件（PLE），其电连接由第一配置数据来控制。 每个PLE包括LUT，其中输入信号的逻辑电平和输出信号的逻辑电平之间的关系由第二配置数据确定，输入LUT的输出信号的FF和MUX 。 MUX包括至少两个开关，每个开关包括第一和第二晶体管。 包括第三配置数据的信号通过第一晶体管输入到第二晶体管的栅极。 LUT的输出信号或FF的输出信号被输入到第二晶体管的源极和漏极之一。
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公开(公告)号：US12142617B2
公开(公告)日：2024-11-12
申请号：US18232424
申请日：2023-08-10
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Takeshi Aoki , Yoshiyuki Kurokawa , Takayuki Ikeda , Hikaru Tamura
IPC: H01L27/146 , G09G3/36 , H01L29/786
Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
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公开(公告)号：US12136465B2
公开(公告)日：2024-11-05
申请号：US17922659
申请日：2021-05-06
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Takeshi Aoki , Yoshiyuki Kurokawa , Munehiro Kozuma , Takuro Kanemura , Tatsunori Inoue
Abstract: A semiconductor device with a small circuit area and low power consumption is provided. The semiconductor device includes first to fourth cells, a current mirror circuit, and first to fourth wirings, and the first to fourth cells each include a first transistor, a second transistor, and a capacitor. In each of the first to fourth cells, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. The first wiring is electrically connected to first terminals of the second transistors in the first cell and the second cell, the second wiring is electrically connected to first terminals of the second transistors in the third cell and the fourth cell, the third wiring is electrically connected to second terminals of the capacitors in the first cell and the third cell, and the fourth wiring is electrically connected to second terminals of the capacitors in the second cell and the fourth cell. The current mirror circuit is electrically connected to the first wiring and the second wiring.
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公开(公告)号：US11908947B2
公开(公告)日：2024-02-20
申请号：US17628091
申请日：2020-07-27
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Munehiro Kozuma , Takahiko Ishizu , Takeshi Aoki , Masashi Fujita , Kazuma Furutani , Kousuke Sasaki
CPC classification number: H01L29/7869 , G06F7/5443 , G11C7/1069 , G11C7/1096 , G11C7/12 , G11C7/14 , H10B12/50 , H01L27/1225
Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a CPU and an accelerator. The accelerator includes a first memory circuit and an arithmetic circuit. The first memory circuit includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The arithmetic circuit includes a second transistor. The second transistor includes a semiconductor layer containing silicon in a channel formation region. The first transistor and the second transistor are provided to be stacked. The CPU includes a CPU core including a flip-flop provided with a backup circuit. The backup circuit includes a third transistor. The third transistor includes a semiconductor layer containing a metal oxide in a channel formation region.
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公开(公告)号：US11799430B2
公开(公告)日：2023-10-24
申请号：US17635268
申请日：2020-08-11
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Kei Takahashi , Takeshi Aoki , Munehiro Kozuma , Takayuki Ikeda
CPC classification number: H03F3/45179 , H01L27/1207 , H03K5/2472 , H01L27/1211 , H02J7/0029
Abstract: A novel comparison circuit, a novel amplifier circuit, a novel battery control circuit, a novel battery protection circuit, a power storage device, a semiconductor device, an electric device, and the like are provided. In a semiconductor device, one of a source and a drain of a first transistor is electrically connected to one of a source and a drain of a second transistor and one of a source and a drain of a third transistor; the other of the source and the drain of the third transistor is electrically connected to a first output terminal; and the other of the source and the drain of the second transistor is electrically connected to a second output terminal. The semiconductor device has a function of outputting a comparison result of a signal supplied to a gate of the second transistor and a signal supplied to a gate of the third transistor, from the first output terminal and the second output terminal; and a function of changing the potential output from the first output terminal in accordance with the potential applied to a back gate of the first transistor.
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Patent Agency Ranking
公开(公告)号：US11755286B2
公开(公告)日：2023-09-12
申请号：US17359859
申请日：2021-06-28
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shintaro Harada , Yoshiyuki Kurokawa , Takeshi Aoki
IPC: G06F7/544 , G06N3/065 , H01L29/786 , G06N3/04
CPC classification number: G06F7/5443 , G06N3/04 , G06N3/065 , H01L29/7869
Abstract: A semiconductor device capable of performing product-sum operation is provided. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. The semiconductor device retains first analog data and reference analog data in the first memory cell and the second memory cell, respectively. A potential corresponding to second analog data is applied to each of them as a selection signal, whereby current depending on the sum of products of the first analog data and the second analog data is obtained. The offset circuit includes a constant current circuit comprising a transistor and a capacitor. A first terminal of the transistor is electrically connected to a first gate of the transistor and a first terminal of the capacitor. A second gate of the transistor is electrically connected to a second terminal of the capacitor. A voltage between the first terminal and the second gate of the transistor is held in the capacitor, whereby a change in source-drain current of the transistor can be suppressed.
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公开(公告)号：US11610544B2
公开(公告)日：2023-03-21
申请号：US17546696
申请日：2021-12-09
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Shintaro Harada , Yoshiyuki Kurokawa , Takeshi Aoki , Yuki Okamoto , Hiroki Inoue , Koji Kusunoki , Yosuke Tsukamoto , Katsuki Yanagawa , Kei Takahashi , Shunpei Yamazaki
Abstract: An electronic device capable of efficiently recognizing a handwritten character is provided.
The electronic device includes a first circuit, a display portion, and a touch sensor. The first circuit includes a neural network. The display portion includes a flexible display. The touch sensor has the function of outputting an input handwritten character as image information to the first circuit. The first circuit has the function of analyzing the image information and converting the image information into character information, and a function of displaying an image including the character information on the display portion. The analysis is performed by inference through the use of the neural network.-
公开(公告)号：US11264415B2
公开(公告)日：2022-03-01
申请号：US17223208
申请日：2021-04-06
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Takeshi Aoki , Yoshiyuki Kurokawa , Takayuki Ikeda , Hikaru Tamura
IPC: H01L27/146 , G09G3/36 , H01L29/786
Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
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公开(公告)号：US10535691B2
公开(公告)日：2020-01-14
申请号：US15177460
申请日：2016-06-09
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Yoshiyuki Kurokawa , Takayuki Ikeda , Hikaru Tamura , Munehiro Kozuma , Masataka Ikeda , Takeshi Aoki
IPC: H01L27/146 , H04N5/378 , H04N5/374 , H01L29/786 , H01L31/105 , H04N5/361
Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
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公开(公告)号：US10446551B2
公开(公告)日：2019-10-15
申请号：US15467142
申请日：2017-03-23
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Takeshi Aoki
IPC: H01L27/108 , H01L27/105 , H01L27/12 , H01L29/24 , H01L29/786 , H01L27/1156
Abstract: To provide a semiconductor memory device which can be manufactured with high yield and which can achieve higher integration. A pair of memory cells adjacent to each other in the bit line direction is connected to a bit line through a common contact hole. The pair of memory cells adjacent to each other in the bit line direction shares an electrode connected to the bit line. An oxide semiconductor layer included in the memory cell is provided to overlap with a word line and a capacitor line. A transistor and a capacitor included in the memory cell are each provided to overlap with the bit line connected to the memory cell.
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