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公开(公告)号：US20170076820A1
公开(公告)日：2017-03-16
申请号：US15343373
申请日：2016-11-04
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Munehiro Azami , Shou Nagao , Yoshifumi Tanada
CPC classification number: G11C19/28 , G02F1/13306 , G02F1/1333 , G09G3/36 , G09G3/3688 , G09G2310/0286 , G09G2330/021 , H01L27/1214 , H01L27/124
Abstract: A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node α rises. When the potential of the node α reaches (VDD−VthN), the node α became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105.
Abstract translation: 脉冲被输入到TFT 101和104，使得TFT将导通，然后节点α的电位上升。 当节点α的电位达到（VDD-VthN）时，节点α变为浮动状态。 因此，TFT 105然后导通，并且输出节点的电位随着时钟信号达到电平H而上升。另一方面，由于电容107的操作，TFT 105的栅电极的电位进一步上升， 输出节点的电位上升，使得输出节点的电位将高于（VDD + VthN）。 因此，由TFT 105的阈值引起的电压下降，输出节点的电位上升到VDD。
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公开(公告)号：US09496291B2
公开(公告)日：2016-11-15
申请号：US14816124
申请日：2015-08-03
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Munehiro Azami , Shou Nagao , Yoshifumi Tanada
IPC: H01L27/12 , G02F1/133 , G09G3/36 , G11C19/28 , G02F1/1333
CPC classification number: G11C19/28 , G02F1/13306 , G02F1/1333 , G09G3/36 , G09G3/3688 , G09G2310/0286 , G09G2330/021 , H01L27/1214 , H01L27/124
Abstract: A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node α rises. When the potential of the node α reaches (VDD−VthN), the node α became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105.
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公开(公告)号：US09208717B2
公开(公告)日：2015-12-08
申请号：US14155517
申请日：2014-01-15
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hajime Kimura , Yoshifumi Tanada
CPC classification number: G09G3/3225 , G09G3/2022 , G09G3/3233 , G09G3/3266 , G09G3/3283 , G09G3/3291 , G09G2300/0814 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2300/0866 , G09G2300/0876 , G09G2300/088 , G09G2310/027 , G09G2310/061 , G09G2320/0233
Abstract: Brightness irregularities that develop in a light emitting device due to is persion among pixels in the threshold values of TFTs used for supplying electric current to light emitting devices become obstacles to improved image quality of the light emitting device. As an image signal input to a pixel from a source signal line, a desired electric potential is applied to a gate electrode of a TFT for supplying electric current to an EL device, through a TFT having its gate and drain connected to each other. A voltage equal to the TFT threshold value is produced between the source and the drain of the TFT 105. An electric potential in which the image signal is offset by the amount of the threshold value is therefore applied to the gate electrode of the TFT. Further, TFTs are disposed in close proximity to each other within the pixel, so that dispersions in the TFT characteristics do not easily develop. A desired drain current can thus be supplied to the EL device even if there is dispersion in the threshold values of the TFTs among pixels, because this is offset by the threshold value of the TFT.
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公开(公告)号：US09030389B2
公开(公告)日：2015-05-12
申请号：US14298292
申请日：2014-06-06
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Yoshifumi Tanada
CPC classification number: H01L27/124 , G09G3/30 , G09G3/32 , G09G2300/0404 , G09G2300/0426 , G09G2300/0809 , G09G2320/0233 , G09G2320/0242 , G09G2330/02 , H01L27/15 , H01L27/156 , H01L27/3211 , H01L27/3262 , H01L27/3276 , H01L33/62 , H01L2924/0002 , H01L2924/00
Abstract: A display device in which the current load of wirings are distributed and display variations due to voltage drop are suppressed. An active matrix display device of the invention comprises a first current input terminal, a second current input terminal, and a plurality of current supply lines extending parallel to each other. Each current supply line is connected to a plurality of driving transistors in a line. One end of each current supply line is connected to the first current input terminal via a first wiring intersecting with the current supply lines, and the other end thereof is connected to the second current input terminal via a second wiring intersecting with the current supply lines. Accordingly, a current is supplied to each current supply line from both the first and the second current input terminals. The first and the second current input terminals are provided separately from each other.
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公开(公告)号：US20140327008A1
公开(公告)日：2014-11-06
申请号：US14332468
申请日：2014-07-16
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Munehiro Azami , Shou Nagao , Yoshifumi Tanada
IPC: H01L27/12 , G02F1/1333
CPC classification number: G11C19/28 , G02F1/13306 , G02F1/1333 , G09G3/36 , G09G3/3688 , G09G2310/0286 , G09G2330/021 , H01L27/1214 , H01L27/124
Abstract: A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node α rises. When the potential of the node α reaches (VDD−VthN), the node α became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105.
Abstract translation: 脉冲被输入到TFT 101和104，使得TFT将导通，然后节点α的电位上升。 当节点α的电位达到（VDD-VthN）时，节点α变为浮动状态。 因此，TFT 105然后导通，并且输出节点的电位随着时钟信号达到电平H而上升。另一方面，由于电容107的操作，TFT 105的栅电极的电位进一步上升， 输出节点的电位上升，使得输出节点的电位将高于（VDD + VthN）。 因此，由TFT 105的阈值引起的电压下降，输出节点的电位上升到VDD。
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Patent Agency Ranking
公开(公告)号：US20140293207A1
公开(公告)日：2014-10-02
申请号：US14306309
申请日：2014-06-17
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Noriko Miyagi , Masayuki Sakakura , Tatsuya Arao , Ritsuko Nagao , Yoshifumi Tanada
IPC: G02F1/1333
CPC classification number: H01L27/124 , G02F1/133345 , G09G3/3233 , G09G2300/0842 , G09G2300/0861 , H01L23/5228 , H01L27/1222 , H01L27/1248 , H01L27/3276 , H01L27/3279 , H01L33/40 , H01L51/5206 , H01L51/5212 , H01L51/5221 , H01L51/5228 , H01L51/5234 , H01L2251/5315
Abstract: An object of the present invention is to decrease substantial resistance of an electrode such as a transparent electrode or a wiring, and furthermore, to provide a display device for which is possible to apply same voltage to light-emitting elements. In the invention, a auxiliary wiring that is formed in one layer in which a conductive film of a semiconductor element such as an electrode, wiring, a signal line, a scanning line, or a power supply line is connected to an electrode typified by a second electrode, and a wiring. It is preferable that the auxiliary wiring is formed into a conductive film to include low resistive material, especially, formed to include lower resistive material than the resistance of an electrode and a wiring that is required to reduce the resistance.
Abstract translation: 本发明的一个目的是降低诸如透明电极或布线的电极的实质电阻，此外，提供一种可以向发光元件施加相同电压的显示装置。 在本发明中，形成在电极，布线，信号线，扫描线或电源线等半导体元件的导电膜的一层中形成的辅助布线连接到以 第二电极和布线。 优选地，辅助布线形成为包括低电阻材料的导电膜，特别地，形成为包括比电阻的阻抗更低的电阻材料和降低电阻所需的布线。
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公开(公告)号：US20140192098A1
公开(公告)日：2014-07-10
申请号：US14155517
申请日：2014-01-15
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hajime Kimura , Yoshifumi Tanada
IPC: G09G3/32
CPC classification number: G09G3/3225 , G09G3/2022 , G09G3/3233 , G09G3/3266 , G09G3/3283 , G09G3/3291 , G09G2300/0814 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2300/0866 , G09G2300/0876 , G09G2300/088 , G09G2310/027 , G09G2310/061 , G09G2320/0233
Abstract: Brightness irregularities that develop in a light emitting device due to is persion among pixels in the threshold values of TFTs used for supplying electric current to light emitting devices become obstacles to improved image quality of the light emitting device. As an image signal input to a pixel from a source signal line, a desired electric potential is applied to a gate electrode of a TFT for supplying electric current to an EL device, through a TFT having its gate and drain connected to each other. A voltage equal to the TFT threshold value is produced between the source and the drain of the TFT 105. An electric potential in which the image signal is offset by the amount of the threshold value is therefore applied to the gate electrode of the TFT. Further, TFTs are disposed in close proximity to each other within the pixel, so that dispersions in the TFT characteristics do not easily develop. A desired drain current can thus be supplied to the EL device even if there is dispersion in the threshold values of the TFTs among pixels, because this is offset by the threshold value of the TFT.
Abstract translation: 由于在用于向发光器件供给电流的TFT的阈值中的像素之间的像素之间在发光器件中产生的亮度不规则性成为改善发光器件的图像质量的障碍。 作为从源极信号线输入到像素的图像信号，通过其栅极和漏极彼此连接的TFT，将期望的电位施加到用于向EL器件提供电流的TFT的栅电极。 在TFT105的源极和漏极之间产生等于TFT阈值的电压。因此，将图像信号偏移阈值的电位施加到TFT的栅电极。 此外，TFT在像素内彼此靠近地布置，使得TFT特性中的分散体不容易发展。 因此，即使在像素中的TFT的阈值存在色散的情况下，也可以将所需的漏极电流提供给EL器件，因为这被TFT的阈值偏移。
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公开(公告)号：US20140168196A1
公开(公告)日：2014-06-19
申请号：US14186600
申请日：2014-02-21
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Mitsuaki Osame , Aya Anzai , Yoshifumi Tanada , Keisuke Miyagawa , Satoshi Seo , Shunpei Yamazaki
IPC: G09G3/32
CPC classification number: G09G3/32 , G09G3/3233 , G09G3/3258 , G09G3/3266 , G09G3/3291 , G09G2300/043 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/0251 , G09G2310/0256 , G09G2310/027 , G09G2310/061 , G09G2310/08 , G09G2320/043 , G09G2320/045 , H01L33/0041
Abstract: A light emitting device that achieves long life, and which is capable of performing high duty drive, by suppressing initial light emitting element deterioration is provided. Reverse bias application to an EL element (109) is performed one row at a time by forming a reverse bias electric power source line (112) and a reverse bias TFT (108). Reverse bias application can therefore be performed in synchronous with operations for write-in of an image signal, light emission, erasure, and the like. Reverse bias application therefore becomes possible while maintaining a duty equivalent to that of a conventional driving method.
Abstract translation: 提供了通过抑制初始发光元件劣化而实现长寿命并能够进行高占空比驱动的发光器件。 通过形成反向偏置电源线（112）和反向偏压TFT（108），一次对一个EL元件（109）施加反向偏置。 因此，可以与图像信号的写入，发光，擦除等的操作同步地执行反向偏置应用。 因此，在保持与常规驱动方法相同的占空比的情况下，可以实现反向偏置应用。
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公开(公告)号：US20130314304A1
公开(公告)日：2013-11-28
申请号：US13949317
申请日：2013-07-24
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hajime Kimura , Yoshifumi Tanada
CPC classification number: H01L27/3276 , G09G3/20 , G09G3/2011 , G09G3/2022 , G09G3/2077 , G09G3/30 , G09G3/3233 , G09G3/3258 , G09G3/3266 , G09G3/3275 , G09G3/3283 , G09G3/3291 , G09G3/3648 , G09G2300/0408 , G09G2300/0426 , G09G2300/043 , G09G2300/0819 , G09G2300/0842 , G09G2300/0852 , G09G2300/0861 , G09G2310/027 , G09G2310/0286 , G09G2310/08 , G09G2320/0233 , G09G2320/043 , H01L27/3262 , H01L27/3265
Abstract: Display irregularities in light emitting devices, which develop due to dispersions per pixel in the threshold value of TFTs for supplying electric current to light emitting elements, are obstacles to increasing the image quality of the light emitting devices. An electric potential in which the threshold voltage of a TFT (105) is either added to or subtracted from the electric potential of a reset signal line (110) is stored in capacitor means (108). A voltage, in which the corresponding threshold voltage is added to an image signal, is applied to a gate electrode of a TFT (106). TFTs within a pixel are disposed adjacently, and dispersion in the characteristics of the TFTs does not easily develop. The threshold value of the TFT (105) is thus cancelled, even if the threshold values of the TFTs (106) differ per pixel, and a predetermined drain current can be supplied to an EL element (109).
Abstract translation: 由于用于向发光元件提供电流的TFT的阈值中的每像素的分散而发展的发光器件的显示不规则性是增加发光器件的图像质量的障碍。 在电容器装置（108）中存储有将TFT（105）的阈值电压加到或从复位信号线（110）的电位中减去的电位。 将相应的阈值电压加到图像信号上的电压施加到TFT（106）的栅电极。 像素内的TFT相邻配置，TFT的特性的分散不容易发展。 即使TFT（106）的阈值每像素不同，TFT（105）的阈值也被消除，并且可以向EL元件（109）提供预定的漏极电流。
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公开(公告)号：US20130297956A1
公开(公告)日：2013-11-07
申请号：US13874573
申请日：2013-05-01
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Yoshifumi Tanada
CPC classification number: G06F1/3234 , G06F1/32 , G06F1/3243 , G06F1/3253 , G06F9/30079 , G06F9/30083 , G06F13/4068 , Y02D10/151 , Y02D10/152
Abstract: A semiconductor device which can consume less power and a method for driving the semiconductor device can be provided. The semiconductor device includes a processor including a control device and an arithmetic unit, a memory device, an input/output device, and a plurality of bus lines which is a path for transmitting and receiving instructions, addresses, or data between the processor and the memory device, or the processor and the input/output device. A first memory storing each piece of information over the bus line is connected to each of the bus lines, and a second memory storing a status flag relating to information over the bus line is connected to the control device.
Abstract translation: 可以提供能够消耗较少功率的半导体器件和用于驱动半导体器件的方法。 该半导体器件包括处理器，该处理器包括控制装置和运算单元，存储器件，输入/输出装置和多条总线，这些总线是用于在处理器和处理器之间发送和接收指令，地址或数据的路径 存储设备，或处理器和输入/输出设备。 将总线上的每条信息存储在第一存储器中的每个总线上，存储与总线上的信息相关的状态标志的第二存储器连接到控制装置。
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