公开(公告)号：US20160049518A1

公开(公告)日：2016-02-18

申请号：US14920259

申请日：2015-10-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/04 ,  H01L29/51 ,  H01L29/49 ,  H01L27/12 ,  H01L49/02

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L28/60 ,  H01L29/04 ,  H01L29/24 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78648

Abstract: A semiconductor device with high aperture ratio is provided. The semiconductor device includes a nitride insulating film, a transistor over the nitride insulating film, and a capacitor including a pair of electrodes over the nitride insulating film. An oxide semiconductor layer is used for a channel formation region of the transistor and one of the electrodes of the capacitor. A transparent conductive film is used for the other electrode of the capacitor. One electrode of the capacitor is in contact with the nitride insulating film, and the other electrode of the capacitor is electrically connected to one of a source electrode and a drain electrode of the transistor.

Abstract translation: 提供了一种具有高开口率的半导体器件。 半导体器件包括氮化物绝缘膜，氮化物绝缘膜上的晶体管，以及包括氮化物绝缘膜上的一对电极的电容器。 氧化物半导体层用于晶体管的沟道形成区域和电容器的电极之一。 透明导电膜用于电容器的另一个电极。 电容器的一个电极与氮化物绝缘膜接触，并且电容器的另一个电极电连接到晶体管的源电极和漏电极之一。

公开(公告)号：US20150270402A1

公开(公告)日：2015-09-24

申请号：US14657195

申请日：2015-03-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Kosei NODA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1262 ,  H01L29/66969

Abstract: A semiconductor device that is suitable for miniaturization. A method for manufacturing a semiconductor device includes the steps of forming a semiconductor, forming a first conductor over the semiconductor, performing a second process on the first conductor so as to form a conductor according to a first pattern, forming a first insulator over the conductor having the first pattern, forming an opening in the first insulator, performing a third process on the conductor having the first pattern in the opening so as to form a first electrode and a second electrode and to expose the semiconductor, forming a second insulator over the first insulator, an inner wall of the opening, and an exposed portion of the semiconductor, forming a second conductor over the second insulator, and performing a fourth process on the second conductor so as to form a third electrode.

Abstract translation: 适合小型化的半导体器件。 一种制造半导体器件的方法包括以下步骤：形成半导体，在半导体上形成第一导体，在第一导体上执行第二工艺以形成根据第一图案的导体，在导体上形成第一绝缘体 具有第一图案，在第一绝缘体中形成开口，在开口中具有第一图案的导体上进行第三处理，以形成第一电极和第二电极，并暴露半导体，在第 第一绝缘体，开口的内壁和半导体的暴露部分，在第二绝缘体上形成第二导体，并在第二导体上执行第四工艺以形成第三电极。

公开(公告)号：US20150255139A1

公开(公告)日：2015-09-10

申请号：US14637542

申请日：2015-03-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Tamae MORIWAKA ,  Yuta ENDO

IPC: G11C11/24 ,  H01L27/115 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L27/115 ,  G11C7/16 ,  G11C8/14 ,  G11C11/24 ,  G11C11/403 ,  G11C11/4085 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/1156 ,  H01L29/24 ,  H01L29/7869

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≧2, the jth sub memory cell is arranged over the j−1th sub memory cell.

Abstract translation: 提供适于小型化的半导体器件。 提供高度可靠的半导体器件。 提供具有改善的操作速度的半导体器件。 [解决方案]一种半导体器件，包括第一至第C（c是2个或更多个的自然数）子存储单元的存储单元，其中：第j子存储单元包括第一晶体管，第二晶体管和电容器; 包括在第一晶体管中的第一半导体层和包括在第二晶体管中的第二半导体层包括氧化物半导体; 电容器的端子之一电连接到包括在第二晶体管中的栅电极; 包括在第二晶体管中的栅电极电连接到包括在第一晶体管中的源电极和漏极之一; 并且当j≥2时，第j个子存储单元布置在第j-1个子存储单元上。

公开(公告)号：US20140183523A1

公开(公告)日：2014-07-03

申请号：US14134371

申请日：2013-12-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO

IPC: H01L27/12

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L28/60 ,  H01L29/04 ,  H01L29/24 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78648

Abstract: A semiconductor device with high aperture ratio is provided. The semiconductor device includes a nitride insulating film, a transistor over the nitride insulating film, and a capacitor including a pair of electrodes over the nitride insulating film. An oxide semiconductor layer is used for a channel formation region of the transistor and one of the electrodes of the capacitor. A transparent conductive film is used for the other electrode of the capacitor. One electrode of the capacitor is in contact with the nitride insulating film, and the other electrode of the capacitor is electrically connected to one of a source electrode and a drain electrode of the transistor.

Abstract translation: 提供了一种具有高开口率的半导体器件。 半导体器件包括氮化物绝缘膜，氮化物绝缘膜上的晶体管，以及包括氮化物绝缘膜上的一对电极的电容器。 氧化物半导体层用于晶体管的沟道形成区域和电容器的电极之一。 透明导电膜用于电容器的另一个电极。 电容器的一个电极与氮化物绝缘膜接触，并且电容器的另一个电极电连接到晶体管的源电极和漏电极之一。

公开(公告)号：US20130264567A1

公开(公告)日：2013-10-10

申请号：US13911502

申请日：2013-06-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yuta ENDO

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L22/10 ,  H01L23/564 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An object of an embodiment of the present invention is to manufacture a highly-reliable semiconductor device comprising a transistor including an oxide semiconductor, in which change of electrical characteristics is small. In the transistor including an oxide semiconductor, oxygen-excess silicon oxide (SiOX (X>2)) is used for a base insulating layer of a top-gate structure or for a protective insulating layer of a bottom-gate structure. By using the oxygen-excess silicon oxide, oxygen is discharged from the insulating layer, and oxygen deficiency of an oxide semiconductor layer and the interface state density between the oxide semiconductor layer and the base insulating layer or the protective insulating layer can be reduced, so that the highly-reliable semiconductor device in which change of electrical characteristics is small can be manufactured.

公开(公告)号：US20220352378A1

公开(公告)日：2022-11-03

申请号：US17708084

申请日：2022-03-30

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuta ENDO ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L27/108 ,  H01L27/12

Abstract: A semiconductor device that can be highly integrated is provided.
The semiconductor device includes first and second transistors and first and second capacitors. Each of the first and second transistors includes a gate insulator and a gate electrode over an oxide. Each of the first and second capacitors includes a conductor, a dielectric over the conductor, and the oxide. The first and second transistors are provided between the first capacitor and the second capacitor. One of a source and a drain of the first transistor is also used as one of a source and a drain of the second transistor. The other of the source and the drain of the first transistor is also used as one electrode of the first capacitor. The other of the source and the drain of the second transistor is also used as one electrode of the second capacitor. The channel lengths of the first and second transistors are larger than the lengths in a direction parallel to short sides of fourth and fifth conductors.

公开(公告)号：US20210234046A1

公开(公告)日：2021-07-29

申请号：US17048255

申请日：2019-04-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuya KAKEHATA ,  Yuta ENDO

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/66

Abstract: A semiconductor device with high on-state current and high reliability is provided. The semiconductor device includes first to fifth insulators, first to third oxides, and first to fourth conductors; the fifth insulator includes an opening in which the second oxide is exposed; the third oxide is placed in contact with a bottom portion of the opening and a side portion of the opening; the second insulator is placed in contact with the third oxide; the third conductor is provided in contact with the second insulator; the third insulator is placed in contact with a top surface of the third conductor and the second insulator; the fourth conductor is in contact with the third insulator and the top surface of the third conductor and placed in the opening with the third oxide, the second insulator, and the third insulator therebetween; the fourth insulator is in contact with a top surface of the first insulator, a side surface of the first oxide, a side surface of the second oxide, a side surface of the first conductor, a top surface of the first conductor, a side surface of the second conductor, and a top surface of the second conductor; and the third insulator is less likely to pass oxygen and/or hydrogen than the second insulator.

公开(公告)号：US20210175235A1

公开(公告)日：2021-06-10

申请号：US17172153

申请日：2021-02-10

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Yuta ENDO ,  Shuhei NAGATSUKA

IPC: H01L27/108 ,  H01L29/786 ,  H01L49/02 ,  H01L29/24 ,  H01L29/08 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66 ,  H01L21/02 ,  H01L21/465 ,  H01L21/027

Abstract: A semiconductor device including a first oxide including a first region and a second region adjacent to each other and a third region and a fourth region with the first region and the second region sandwiched between the third region and the fourth region, a second oxide over the first region, a first insulator over the second oxide, a first conductor over the first insulator, a second insulator over the second oxide and on side surfaces of the first insulator and the first conductor, a third insulator over the second region and on a side surface of the second insulator, a second conductor over the second region with the third insulator positioned between the second region and the second conductor and on the side surface of the second insulator with the third insulator positioned between the side surface of the second insulator and the second conductor, and a fourth insulator covering the first oxide, the second oxide, the first insulator, the first conductor, the second insulator, the third insulator, and the second conductor and in contact with the third region and the fourth region.

公开(公告)号：US20200343251A1

公开(公告)日：2020-10-29

申请号：US16810902

申请日：2020-03-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Tamae MORIWAKA ,  Yuta ENDO

IPC: H01L27/115 ,  H01L29/786 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/06 ,  G11C7/16 ,  G11C8/14 ,  G11C11/403 ,  G11C11/408 ,  G11C11/24 ,  H01L29/24

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.

公开(公告)号：US20190181159A1

公开(公告)日：2019-06-13

申请号：US16266263

申请日：2019-02-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hideomi SUZAWA ,  Yuta ENDO ,  Kazuya HANAOKA

IPC: H01L27/12 ,  H01L29/786

Abstract: A semiconductor device with reduced parasitic capacitance is provided. The semiconductor device includes a first insulating layer; a first oxide layer over the first insulating layer; a semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer over the semiconductor layer; a second insulating layer over the first insulating layer; a third insulating layer over the second insulating layer, the source electrode layer, and the drain electrode layer; a second oxide layer over the semiconductor layer; a gate insulating layer over the second oxide layer; a gate electrode layer over the gate insulating layer; and a fourth insulating layer over the third insulating layer, the second oxide layer, the gate insulating layer, and the gate electrode layer.