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    Circuit and method for data output in synchronous semiconductor device
    21.
    发明授权
    Circuit and method for data output in synchronous semiconductor device 失效
    同步半导体器件数据输出电路及方法

    公开(公告)号：US06631090B1

    公开(公告)日：2003-10-07

    申请号：US10266789

    申请日：2002-10-08

    申请人： Jin-Seok Kwak ,  Seong-Jin Jang

    发明人： Jin-Seok Kwak ,  Seong-Jin Jang

    IPC分类号： G11C1604

    CPC分类号： G11C7/106 ,  G11C7/1018 ,  G11C7/1051 ,  G11C2207/002

    摘要： A data output circuit and method in a synchronous semiconductor device are described. The semiconductor device is preferably a wave pipelined synchronous semiconductor device. A first-stage or former-stage latch unit receives a first bit of a group of data bits to be output. A second-stage or latter-stage latch unit receives a second bit of the group of data bits. A buffering unit is interposed between the first and second stage latch units. The buffering unit receives the second bit from the second-stage latch unit and forwards the second bit to the first-stage latch unit.

    摘要翻译： 描述同步半导体器件中的数据输出电路和方法。 半导体器件优选地是波长流水线同步半导体器件。 第一级或前级锁存单元接收要输出的一组数据位的第一位。 第二级或后级锁存单元接收该组数据位的第二位。 缓冲单元插入在第一和第二级闩锁单元之间。 缓冲单元从第二级锁存单元接收第二位，并将第二位转发到第一级锁存单元。

    Data output buffer for memory device
    22.
    发明授权
    Data output buffer for memory device 失效
    存储器件的数据输出缓冲器

    公开(公告)号：US5844846A

    公开(公告)日：1998-12-01

    申请号：US44172

    申请日：1998-03-19

    申请人： Seong-Jin Jang

    发明人： Seong-Jin Jang

    IPC分类号： G06F1/32 ,  G06F1/04 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/417 ,  H03K19/0175 ,  H03K19/094 ,  G11C7/00 ,  H03K17/16

    CPC分类号： G11C7/1051

    摘要： A data output buffer for a memory device having a memory chip includes a detection unit for detecting an external output data and outputting a detection data, a clock signal adjusting unit coupled to the detection unit for comparing the detection data from the detection unit and a data outputted from the memory chip in accordance with an externally applied clock signal and outputting a first signal and a second signal, and an output buffer unit coupled to the clock signal adjusting unit and outputting a data in accordance with the first signal and the second signal.

    摘要翻译： 一种用于具有存储芯片的存储器件的数据输出缓冲器，包括检测单元，用于检测外部输出数据并输出检测数据;时钟信号调整单元，耦合到检测单元，用于比较来自检测单元的检测数据和数据 根据外部施加的时钟信号从存储器芯片输出并输出第一信号和第二信号;以及输出缓冲单元，耦合到时钟信号调整单元，并根据第一信号和第二信号输出数据。

    Semiconductor memory device for controlling operation of delay-locked loop circuit
    23.
    发明授权
    Semiconductor memory device for controlling operation of delay-locked loop circuit 有权
    用于控制延迟锁定环路电路的半导体存储器件

    公开(公告)号：US08730751B2

    公开(公告)日：2014-05-20

    申请号：US13467188

    申请日：2012-05-09

    申请人： Jun-Bae Kim ,  Seong-Jin Jang ,  Young-Uk Chang ,  Sin-Ho Kim

    发明人： Jun-Bae Kim ,  Seong-Jin Jang ,  Young-Uk Chang ,  Sin-Ho Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/02 ,  G11C7/222 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  H03L7/0812 ,  H03L7/0891

    摘要： A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit is provided. The semiconductor memory device includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obtaining a locked state. A control unit controls the DLL circuit to constantly maintain the locked state during an updating period of an auto-refresh period of an auto-refresh operation for refreshing memory banks.

    摘要翻译： 提供一种用于控制延迟锁定环（DLL）电路的操作的半导体存储器件。 半导体存储器件包括DLL电路，其接收外部时钟信号，并且对外部时钟信号和内部时钟信号执行锁定操作，由此获得锁定状态。 控制单元控制DLL电路在刷新存储体的自动刷新操作的自动刷新周期的更新周期期间始终保持锁定状态。

    SEMICONDUCTOR MEMORY DEVICE FOR CONTROLLING OPERATION OF DELAY-LOCKED LOOP CIRCUIT
    25.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE FOR CONTROLLING OPERATION OF DELAY-LOCKED LOOP CIRCUIT 有权
    用于控制延迟环路电路操作的半导体存储器件

    公开(公告)号：US20120218848A1

    公开(公告)日：2012-08-30

    申请号：US13467188

    申请日：2012-05-09

    申请人： JUN-BAE KIM ,  Seong-Jin Jang ,  Young-Uk Chang ,  Sin-Ho Kim

    发明人： JUN-BAE KIM ,  Seong-Jin Jang ,  Young-Uk Chang ,  Sin-Ho Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/02 ,  G11C7/222 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  H03L7/0812 ,  H03L7/0891

    摘要： A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit is provided. The semiconductor memory device includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obtaining a locked state. A control unit controls the DLL circuit to constantly maintain the locked state during an updating period of an auto-refresh period of an auto-refresh operation for refreshing memory banks.

    摘要翻译： 提供一种用于控制延迟锁定环（DLL）电路的操作的半导体存储器件。 半导体存储器件包括DLL电路，其接收外部时钟信号，并且对外部时钟信号和内部时钟信号执行锁定操作，由此获得锁定状态。 控制单元控制DLL电路在刷新存储体的自动刷新操作的自动刷新周期的更新周期期间始终保持锁定状态。

    Semiconductor memory device having improved local input/output line precharge scheme
    26.
    发明授权
    Semiconductor memory device having improved local input/output line precharge scheme 有权
    具有改进的本地输入/输出线预充电方案的半导体存储器件

    公开(公告)号：US08213248B2

    公开(公告)日：2012-07-03

    申请号：US12659328

    申请日：2010-03-04

    申请人： Jong-Ho Moon ,  Seong-Jin Jang

    发明人： Jong-Ho Moon ,  Seong-Jin Jang

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1048 ,  G11C11/4096

    摘要： A data path circuit of a semiconductor memory device includes: a bit line sense amplifier driven by a first power supply voltage; a local input/output line sense amplifier; a column selecting unit operatively connecting a pair of bit lines connected to the bit line sense amplifier and a pair of local input/output lines connected to the local input/output line sense amplifier in response to a column selection signal; and a local input/output line precharge unit precharging the pair of local input/output lines with a second power supply voltage different from the first power supply voltage during a period for which the column selection signal is in an inactive state.

    摘要翻译： 半导体存储器件的数据路径电路包括：由第一电源电压驱动的位线读出放大器; 本地输入/输出线路读出放大器; 列选择单元，可操作地连接连接到位线读出放大器的一对位线和响应于列选择信号连接到本地输入/输出线读出放大器的一对本地输入/输出线; 以及本地输入/输出线预充电单元，在列选择信号处于非活动状态的期间，用与第一电源电压不同的第二电源电压对一对本地输入/输出线进行预充电。

    Semiconductor memory device and latency signal generating method thereof
    27.
    发明授权
    Semiconductor memory device and latency signal generating method thereof 有权
    半导体存储器件及其等待时间信号产生方法

    公开(公告)号：US07778094B2

    公开(公告)日：2010-08-17

    申请号：US12219816

    申请日：2008-07-29

    申请人： Kwang-II Park ,  Young-Hyun Jun ,  Seong-Jin Jang ,  Ho-Young Song

    发明人： Kwang-II Park ,  Young-Hyun Jun ,  Seong-Jin Jang ,  Ho-Young Song

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C7/1072

    摘要： A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.

    摘要翻译： 公开了等待信号产生方法和相应的半导体存储器件。 这种方法包括：接收半导体存储器件的时钟信号; 接收模式表征信号; 提供DQS; 以及根据模式表征信号调整DQS的前导码状态的持续时间，以促进DQS的选通状态与时钟信号的一致性。

    Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device
    28.
    发明授权
    Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device 有权
    在双泵浦地址方案存储器件中使用扩展有效地址窗口采样有效命令的电路和方法

    公开(公告)号：US07656742B2

    公开(公告)日：2010-02-02

    申请号：US12128464

    申请日：2008-05-28

    申请人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

    发明人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

    IPC分类号： G11C8/00

    CPC分类号： G06F12/02 ,  G11C7/1078 ,  G11C7/109

    摘要： Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.

    摘要翻译： 提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。 扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

    Semiconductor devices, a system including semiconductor devices and methods thereof
    29.
    发明申请
    Semiconductor devices, a system including semiconductor devices and methods thereof 有权
    半导体器件，包括半导体器件的系统及其方法

    公开(公告)号：US20090267813A1

    公开(公告)日：2009-10-29

    申请号：US12453109

    申请日：2009-04-29

    申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

    发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

    IPC分类号： H03M7/00

    CPC分类号： H03K19/00346 ,  H04L25/03866 ,  H04L25/14 ,  H04L25/4908

    摘要： Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

    摘要翻译： 提供半导体器件，包括所述半导体器件的系统及其方法。 半导体器件的示例可以接收被调度用于发送的数据，对接收到的数据内的比特顺序进行加扰，按照给定的伪随机序列排列的加扰顺序。 所接收的数据可以是平衡的，使得等于第一逻辑电平的接收数据内的第一比特数与等于第二逻辑电平的接收数据中的第二比特数之间的差异低于阈值。 然后可以发送平衡和加扰的接收数据。 示例半导体器件可以以任何顺序执行加扰和平衡操作。 类似地，在接收端，另一个半导体器件可以通过对发送的数据进行解扰和不平衡来解码原始数据。 可以基于发送的数据被加扰和平衡的顺序以顺序执行解扰和不平衡操作。

    Small swing signal receiver for low power consumption and semiconductor device including the same
    30.
    发明授权
    Small swing signal receiver for low power consumption and semiconductor device including the same 有权
    用于低功耗的小型摆动信号接收器和包括它的半导体器件

    公开(公告)号：US07463072B2

    公开(公告)日：2008-12-09

    申请号：US11566651

    申请日：2006-12-04

    申请人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

    发明人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

    IPC分类号： H03B1/00

    CPC分类号： H03K19/0013 ,  H03K19/018521

    摘要： A circuit including a voltage boost circuit coupled to a first node and a second node, and configured to apply a boosted first node voltage to the second node; and an inverter circuit coupled to the first node, the second node, and a third node, and configured to generate a signal on the third node in response to the signals on the first node and the second node.

    摘要翻译： 一种电路，包括耦合到第一节点和第二节点的升压电路，并且被配置为将升压的第一节点电压施加到所述第二节点; 以及反相器电路，其耦合到所述第一节点，所述第二节点和第三节点，并且被配置为响应于所述第一节点和所述第二节点上的信号而在所述第三节点上生成信号。