公开(公告)号：US07911028B2

公开(公告)日：2011-03-22

申请号：US12183077

申请日：2008-07-31

申请人： Shian-Jyh Lin ,  Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng

发明人： Shian-Jyh Lin ,  Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng

IPC分类号： H01L29/94

CPC分类号： H01L28/75 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66181 ,  H01L29/785

摘要： A semiconductor device including a metallic compound Hfx1Moy1Nz1 as an electrode. The work function of the electrode can be modulated by doping the metallic compound with dopants including nitrogen, silicon or germanium. The metallic compound of the present invention is applicable to PMOS, NMOS, CMOS transistors and capacitors.

摘要翻译： 一种半导体器件，包括金属化合物Hfx1Moy1Nz1作为电极。 电极的功函数可以通过掺杂含有氮，硅或锗的掺杂剂的金属化合物来调节。 本发明的金属化合物可应用于PMOS，NMOS，CMOS晶体管和电容器。

公开(公告)号：US07619271B2

公开(公告)日：2009-11-17

申请号：US11940547

申请日：2007-11-15

申请人： Shian-Jyh Lin ,  Chien-Li Cheng

发明人： Shian-Jyh Lin ,  Chien-Li Cheng

IPC分类号： H01L29/94

CPC分类号： H01L29/945 ,  H01L27/10823 ,  H01L27/10867 ,  H01L29/66181

摘要： A deep trench device with a single sided connecting structure. The device comprises a substrate having a trench therein. A buried trench capacitor is disposed in a lower portion of the trench. An asymmetric collar insulator is disposed on an upper portion of the sidewall of the trench. A connecting structure is disposed in the upper portion of the trench, comprising an epitaxial silicon layer disposed on and adjacent to a relatively low portion of the asymmetric collar insulator and a connecting member disposed between the epitaxial silicon layer and a relatively high portion of the asymmetric collar insulator. A conductive layer is disposed between the relatively high and low portions of the asymmetric collar insulator, to electrically connect the buried trench capacitor and the connecting structure. A cap layer is disposed on the connecting structure. A fabrication method for a deep trench device is also disclosed.

摘要翻译： 具有单面连接结构的深沟槽装置。 该装置包括其中具有沟槽的衬底。 埋沟槽电容器设置在沟槽的下部。 不对称环形绝缘体设置在沟槽的侧壁的上部。 连接结构设置在沟槽的上部，包括设置在不对称环形绝缘体的相对较低部分上并与其相邻的外延硅层，以及设置在外延硅层和不对称的较高部分之间的连接构件 项圈绝缘子。 导电层设置在不对称环形绝缘体的相对较高和较低的部分之间，以电连接埋入沟槽电容器和连接结构。 盖层设置在连接结构上。 还公开了一种深沟槽器件的制造方法。

公开(公告)号：US20090047766A1

公开(公告)日：2009-02-19

申请号：US11970465

申请日：2008-01-07

申请人： Shian-Jyh Lin

发明人： Shian-Jyh Lin

IPC分类号： H01L21/336 ,  H01L21/76

CPC分类号： H01L27/10876 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823481

摘要： A method for fabricating recess channel MOS transistors of the present invention utilizes a lithography process to form trenches in the recess channel MOS transistors after finishing a STI process. Furthermore, the method of the present invention can make the critical dimension variation to be controlled in a range required in the precision semiconductor process. Therefore, the short problem between the transistors can be avoided.

摘要翻译： 本发明的凹槽MOS晶体管的制造方法利用光刻工艺在完成STI工艺之后在凹槽MOS晶体管中形成沟槽。 此外，本发明的方法可以使临界尺寸变化被控制在精密半导体工艺所需的范围内。 因此，可以避免晶体管之间的短暂问题。

公开(公告)号：US20090032856A1

公开(公告)日：2009-02-05

申请号：US11963850

申请日：2007-12-24

申请人： Lee-Jen Chen ,  Shian-Jyh Lin

发明人： Lee-Jen Chen ,  Shian-Jyh Lin

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/105 ,  H01L27/10861 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

摘要： A manufacturing method of a volatile memory device is provided. The manufacturing method includes steps as follows. A sacrificial layer is formed in an area which is predetermined for forming a metal gate. Then, a thermal treatment process or other high temperature processes are performed in a peripheral circuit region. Next, a fabricating process of the metal gate is performed. Thus, the volatile memory device which has a lower contact resistance and a higher driving ability of the device can be produced, and thereby poor thermal stability and pollution of metal diffusion can be avoided.

摘要翻译： 提供了一种易失性存储器件的制造方法。 制造方法包括以下步骤。 牺牲层形成在预定的用于形成金属栅极的区域中。 然后，在外围电路区域中进行热处理工艺或其它高温处理。 接下来，执行金属栅极的制造工艺。 因此，可以产生具有较低接触电阻和较高驱动能力的易失性存储器件，从而可以避免热稳定性差和金属扩散污染。

公开(公告)号：US20070246755A1

公开(公告)日：2007-10-25

申请号：US11696163

申请日：2007-04-03

申请人： Pei-Ing Lee ,  Chien-Li Cheng ,  Shian-Jyh Lin

发明人： Pei-Ing Lee ,  Chien-Li Cheng ,  Shian-Jyh Lin

IPC分类号： H01L29/76 ,  H01L21/8234

CPC分类号： H01L27/10861 ,  H01L27/0629 ,  H01L27/10876

摘要： A method of fabricating self-aligned gate trench utilizing TTO poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide (TTO) that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.

摘要翻译： 公开了一种使用TTO多隔离件制造自对准栅极沟槽的方法。 提供其上具有衬垫氧化物层和衬垫氮化物层的半导体衬底。 多个沟槽电容器嵌入在半导体衬底的存储器阵列区域中。 每个沟槽电容器具有从半导体衬底的主表面挤出的沟槽顶部氧化物（TTO）。 聚合物间隔物形成在挤出TTO的两个相对侧上，并且在氧化后用作蚀刻硬掩模，用于蚀刻紧邻沟槽电容器的凹陷栅极沟槽。

公开(公告)号：US20070131998A1

公开(公告)日：2007-06-14

申请号：US11679087

申请日：2007-02-26

申请人： Shian-Jyh Lin ,  Sheng-Tsung Chen ,  Neng-Tai Shih

发明人： Shian-Jyh Lin ,  Sheng-Tsung Chen ,  Neng-Tai Shih

IPC分类号： H01L29/94

CPC分类号： H01L27/10876 ,  H01L27/10841 ,  H01L27/10867

摘要： A vertical transistor device and fabrication method thereof are provided, the vertical transistor device comprising a substrate having a deep trench. A capacitor is disposed in a lower portion of the deep trench. A conductive structure is disposed on the capacitor inside the deep trench. An epitaxial layer, having an epitaxial sidewall region, is disposed on the substrate. A vertical gate structure is disposed on the conductive structure and adjacent to the epitaxial sidewall region of the epitaxial layer.

摘要翻译： 提供了一种垂直晶体管器件及其制造方法，该垂直晶体管器件包括具有深沟槽的衬底。 电容器设置在深沟槽的下部。 导电结构设置在深沟槽内的电容器上。 具有外延侧壁区域的外延层设置在基板上。 垂直栅极结构设置在导电结构上并与外延层的外延侧壁区相邻。

公开(公告)号：US07078307B2

公开(公告)日：2006-07-18

申请号：US10940761

申请日：2004-09-15

申请人： Shian-Jyh Lin ,  Chia-Sheng Yu

发明人： Shian-Jyh Lin ,  Chia-Sheng Yu

IPC分类号： H01L21/20

CPC分类号： H01L27/10867

摘要： A method for manufacturing a single-ended buried strap used in semiconductor devices is disclosed. According to the present invention, a trench capacitor structure is formed in a semiconductor substrate, wherein the trench capacitor structure has a contact surface lower than a surface of the semiconductor substrate such that a recess is formed. Then, an insulative layer is formed on a sidewall of the recess. Next, impurities are implanted into a portion of the insulative layer, and the impurity-containing insulative layer is thereafter removed such that at least a portion of the contact surface and a portion of sidewall of the recess are exposed. A buried strap is sequentially formed on the exposed sidewall of the recess to be in contact with the exposed contact surface.

摘要翻译： 公开了一种制造半导体器件中使用的单端掩埋带的方法。 根据本发明，在半导体衬底中形成沟槽电容器结构，其中沟槽电容器结构具有比半导体衬底的表面低的接触表面，从而形成凹部。 然后，在凹部的侧壁上形成绝缘层。 接下来，将杂质注入到绝缘层的一部分中，然后去除含杂质的绝缘层，使得接触表面的至少一部分和凹部的侧壁的一部分露出。 在凹部的暴露的侧壁上依次形成埋设的带子，以与暴露的接触表面接触。

公开(公告)号：US20060033041A1

公开(公告)日：2006-02-16

申请号：US11203002

申请日：2005-08-11

申请人： Shian-Jyh Lin ,  Yuan-Song Tai

发明人： Shian-Jyh Lin ,  Yuan-Song Tai

IPC分类号： B01D59/44

CPC分类号： H01J37/05 ,  H01J37/244 ,  H01J2237/05 ,  H01J2237/24405 ,  H01J2237/2446 ,  H01J2237/24485 ,  H01J2237/24507 ,  H01J2237/31703

摘要： An ion beam energy monitor system and method thereof. A physical field generator generates a physical field in a direction not parallel to an ion beam, refracting the ion beam, and a receiving device located on the path of the refracted ion beam receives the ion beam and calculates the energy thereof according to a collision distribution of ions of the ion beam. The output energy of the ion beam is thus being well adjusted.

摘要翻译： 一种离子束能量监测系统及其方法。 物理场发生器在不平行于离子束的方向上产生物理场，折射离子束，位于折射离子束路径上的接收装置接收离子束并根据碰撞分布计算其能量 的离子束离子。 因此，离子束的输出能量被很好地调节。

公开(公告)号：US20050208727A1

公开(公告)日：2005-09-22

申请号：US10871619

申请日：2004-06-18

申请人： Shian-Jyh Lin ,  Yu-Sheng Hsu ,  Chung-Yuan Lee

发明人： Shian-Jyh Lin ,  Yu-Sheng Hsu ,  Chung-Yuan Lee

IPC分类号： H01L21/033 ,  H01L21/20 ,  H01L21/308 ,  H01L21/311 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94

CPC分类号： H01L27/1087 ,  H01L21/0337 ,  H01L21/3086 ,  H01L29/66181 ,  H01L29/945

摘要： A method for forming a bottle trench. First, a substrate covered by a photoresist layer is rotated to a specific angle prior to performance of lithography, thereby forming a rectangular opening in the photoresist layer and exposing the substrate, in which edges of the rectangular opening are substantially parallel to the {110} plane of the substrate due to the rotation of the substrate. Next, the exposed substrate is etched to form a trench therein, in which the sidewall surface of the trench is the {110} plane of the substrate. Finally, isotropic etching is performed on the substrate of the lower portion of the trench using an etching shield layer formed on the sidewall of the upper portion of the trench as an etching mask, to form the bottle trench. The invention also discloses a method of fabricating a bottle trench capacitor.

公开(公告)号：US20050116275A1

公开(公告)日：2005-06-02

申请号：US10707264

申请日：2003-12-02

申请人： Shian-Jyh Lin ,  Sam Liao ,  Chia-Sheng Yu

发明人： Shian-Jyh Lin ,  Sam Liao ,  Chia-Sheng Yu

IPC分类号： H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L29/66181 ,  H01L29/945

摘要： Afin-type trench capacitor structure includes a buried plate diffused into a silicon substrate. The buried plate, which surrounds a bottle-shaped lower portion of the trench capacitor structure, is electrically connected to an upwardly extending annular poly electrode, thereby enabling the buried plate and the annular poly electrode to constitute a large-area capacitor electrode of the trench capacitor structure. A capacitor storage node consisting of a surrounding conductive layer, a central conductive layer and a collar conductive layer encompasses the upwardly extending annular poly electrode. A first capacitor dielectric layer isolates the capacitor storage node from the buried plate. A second capacitor dielectric layer and a third capacitor dielectric layer isolate the upwardly extending annular poly electrode from the capacitor storage node.

摘要翻译： Afin型沟槽电容器结构包括扩散到硅衬底中的掩埋板。 包围沟槽电容器结构的瓶形下部的掩埋板电连接到向上延伸的环状聚电极，从而使掩埋板和环形聚电极能够构成沟槽的大面积电容器电极 电容器结构。 由周围的导电层，中心导电层和环状导电层组成的电容器存储节点包围向上延伸的环形多晶电极。 第一电容器电介质层将电容器存储节点与掩埋板隔离。 第二电容器电介质层和第三电容器介电层将电容器存储节点上的向上延伸的环形多晶硅电极隔离。