公开(公告)号：US20110226736A1

公开(公告)日：2011-09-22

申请号：US13118604

申请日：2011-05-31

Applicant: Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng ,  Chung-Yuan Lee ,  Shian-Jyh Lin

Inventor： Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng ,  Chung-Yuan Lee ,  Shian-Jyh Lin

IPC: C23F1/02 ,  C23F1/26

CPC classification number: C23F1/26 ,  H01L21/32134

Abstract: A method of patterning a metal alloy material layer having hafnium and molybdenum. The method includes forming a patterned mask layer on a metal alloy material layer having hafnium and molybdenum on a substrate. The patterned mask layer is used as a mask and an etching process is performed using an etchant on the metal alloy material layer having hafnium and molybdenum so as to form a metal alloy layer having hafnium and molybdenum. The etchant includes at least nitric acid, hydrofluoric acid and sulfuric acid. The patterned mask layer is removed.

Abstract translation: 图案化具有铪和钼的金属合金材料层的方法。 该方法包括在基板上的具有铪和钼的金属合金材料层上形成图案化掩模层。 图案化掩模层用作掩模，并且使用具有铪和钼的金属合金材料层上的蚀刻剂进行蚀刻处理，以形成具有铪和钼的金属合金层。 蚀刻剂至少包括硝酸，氢氟酸和硫酸。 去除图案化的掩模层。

公开(公告)号：US07943513B2

公开(公告)日：2011-05-17

申请号：US12506394

申请日：2009-07-21

Applicant: Shian-Jyh Lin

Inventor： Shian-Jyh Lin

IPC: H01L21/44

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/15311 ,  Y10S438/928 ,  H01L2224/05552

Abstract: A conductive through connection having a body layer and a metal layer is disposed on a semiconductor device, which the metal layer is on a top of body layer and includes a conductive body configured to penetrate the body layer and the metal layer. The width/diameter of one end of the conductive body is larger than that of another end thereof. The shape of these two ends of the body layer can be rectangular or circular.

Abstract translation: 具有主体层和金属层的导电贯穿连接设置在半导体器件上，金属层位于主体层的顶部，并且包括被构造成穿透体层和金属层的导电体。 导电体的一端的宽度/直径大于其另一端的宽度/直径。 体层的这两端的形状可以是矩形或圆形。

公开(公告)号：US07932555B2

公开(公告)日：2011-04-26

申请号：US11949788

申请日：2007-12-04

Applicant: Pei-Ing Lee ,  Shian-Jyh Lin

Inventor： Pei-Ing Lee ,  Shian-Jyh Lin

IPC: H01L29/66

CPC classification number: H01L27/1087 ,  H01L27/10841

Abstract: A transistor structure includes a gate trench. The gate trench includes a bottle-shape bottom. The bottle-shape bottom includes a first conductive material wider than its top. The top includes a second material in a substrate, a gate structure on the gate trench and electrically connected to the first conductive material, a source/drain doping region adjacent to the gate trench and a gate channel between the source/drain doping region.

Abstract translation: 晶体管结构包括栅极沟槽。 栅极沟槽包括瓶形底部。 瓶形底部包括比其顶部更宽的第一导电材料。 顶部包括衬底中的第二材料，栅极沟槽上的栅极结构和电连接到第一导电材料，与栅极沟槽相邻的源极/漏极掺杂区域和源极/漏极掺杂区域之间的栅极沟道。

公开(公告)号：US07911028B2

公开(公告)日：2011-03-22

申请号：US12183077

申请日：2008-07-31

Applicant: Shian-Jyh Lin ,  Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng

Inventor： Shian-Jyh Lin ,  Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng

IPC: H01L29/94

CPC classification number: H01L28/75 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66181 ,  H01L29/785

Abstract: A semiconductor device including a metallic compound Hfx1Moy1Nz1 as an electrode. The work function of the electrode can be modulated by doping the metallic compound with dopants including nitrogen, silicon or germanium. The metallic compound of the present invention is applicable to PMOS, NMOS, CMOS transistors and capacitors.

Abstract translation: 一种半导体器件，包括金属化合物Hfx1Moy1Nz1作为电极。 电极的功函数可以通过掺杂含有氮，硅或锗的掺杂剂的金属化合物来调节。 本发明的金属化合物可应用于PMOS，NMOS，CMOS晶体管和电容器。

公开(公告)号：US07619271B2

公开(公告)日：2009-11-17

申请号：US11940547

申请日：2007-11-15

Applicant: Shian-Jyh Lin ,  Chien-Li Cheng

Inventor： Shian-Jyh Lin ,  Chien-Li Cheng

IPC: H01L29/94

CPC classification number: H01L29/945 ,  H01L27/10823 ,  H01L27/10867 ,  H01L29/66181

Abstract: A deep trench device with a single sided connecting structure. The device comprises a substrate having a trench therein. A buried trench capacitor is disposed in a lower portion of the trench. An asymmetric collar insulator is disposed on an upper portion of the sidewall of the trench. A connecting structure is disposed in the upper portion of the trench, comprising an epitaxial silicon layer disposed on and adjacent to a relatively low portion of the asymmetric collar insulator and a connecting member disposed between the epitaxial silicon layer and a relatively high portion of the asymmetric collar insulator. A conductive layer is disposed between the relatively high and low portions of the asymmetric collar insulator, to electrically connect the buried trench capacitor and the connecting structure. A cap layer is disposed on the connecting structure. A fabrication method for a deep trench device is also disclosed.

Abstract translation: 具有单面连接结构的深沟槽装置。 该装置包括其中具有沟槽的衬底。 埋沟槽电容器设置在沟槽的下部。 不对称环形绝缘体设置在沟槽的侧壁的上部。 连接结构设置在沟槽的上部，包括设置在不对称环形绝缘体的相对较低部分上并与其相邻的外延硅层，以及设置在外延硅层和不对称的较高部分之间的连接构件 项圈绝缘子。 导电层设置在不对称环形绝缘体的相对较高和较低的部分之间，以电连接埋入沟槽电容器和连接结构。 盖层设置在连接结构上。 还公开了一种深沟槽器件的制造方法。

公开(公告)号：US20090134442A1

公开(公告)日：2009-05-28

申请号：US12103590

申请日：2008-04-15

Applicant: Shian-Jyh Lin ,  Yuan Tsung Chang ,  Shun-Fu Chen ,  Chung-Tze Lin ,  Chung-Yuan Lee ,  Tse Chuan Kuo

Inventor： Shian-Jyh Lin ,  Yuan Tsung Chang ,  Shun-Fu Chen ,  Chung-Tze Lin ,  Chung-Yuan Lee ,  Tse Chuan Kuo

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L29/66621 ,  H01L27/10867 ,  H01L27/10876

Abstract: A method for forming a recessed channel device includes providing a substrate with a plurality of trench capacitors formed therein, each of the trench capacitors including a plug protruding above the substrate; forming a spacer on each of the plugs; forming a plurality of trench isolations along a first direction in the substrate adjacent to the trench capacitors so as to define an active area exposing the substrate; removing a portion of the substrate by using the spacers and the trench isolations as a mask to form a recessed channel; and trimming the recessed channel so that a surface profile of the recessed channel presents a three-dimensional shape. A recessed channel device with a rounded channel profile is also provided.

Abstract translation: 用于形成凹陷通道器件的方法包括：提供其上形成有多个沟槽电容器的衬底，每个沟槽电容器包括突出在衬底上方的插头; 在每个插头上形成间隔件; 在与所述沟槽电容器相邻的所述衬底中沿着第一方向形成多个沟槽隔离，以限定暴露所述衬底的有源区; 通过使用间隔物和沟槽隔离物作为掩模去除衬底的一部分以形成凹陷沟道; 并且修整凹陷通道，使得凹陷通道的表面轮廓呈现三维形状。 还提供了具有圆形通道轮廓的凹槽通道装置。

公开(公告)号：US20090047766A1

公开(公告)日：2009-02-19

申请号：US11970465

申请日：2008-01-07

Applicant: Shian-Jyh Lin

Inventor： Shian-Jyh Lin

IPC: H01L21/336 ,  H01L21/76

CPC classification number: H01L27/10876 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823481

Abstract: A method for fabricating recess channel MOS transistors of the present invention utilizes a lithography process to form trenches in the recess channel MOS transistors after finishing a STI process. Furthermore, the method of the present invention can make the critical dimension variation to be controlled in a range required in the precision semiconductor process. Therefore, the short problem between the transistors can be avoided.

Abstract translation: 本发明的凹槽MOS晶体管的制造方法利用光刻工艺在完成STI工艺之后在凹槽MOS晶体管中形成沟槽。 此外，本发明的方法可以使临界尺寸变化被控制在精密半导体工艺所需的范围内。 因此，可以避免晶体管之间的短暂问题。

公开(公告)号：US20090032856A1

公开(公告)日：2009-02-05

申请号：US11963850

申请日：2007-12-24

Applicant: Lee-Jen Chen ,  Shian-Jyh Lin

Inventor： Lee-Jen Chen ,  Shian-Jyh Lin

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/105 ,  H01L27/10861 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

Abstract: A manufacturing method of a volatile memory device is provided. The manufacturing method includes steps as follows. A sacrificial layer is formed in an area which is predetermined for forming a metal gate. Then, a thermal treatment process or other high temperature processes are performed in a peripheral circuit region. Next, a fabricating process of the metal gate is performed. Thus, the volatile memory device which has a lower contact resistance and a higher driving ability of the device can be produced, and thereby poor thermal stability and pollution of metal diffusion can be avoided.

Abstract translation: 提供了一种易失性存储器件的制造方法。 制造方法包括以下步骤。 牺牲层形成在预定的用于形成金属栅极的区域中。 然后，在外围电路区域中进行热处理工艺或其它高温处理。 接下来，执行金属栅极的制造工艺。 因此，可以产生具有较低接触电阻和较高驱动能力的易失性存储器件，从而可以避免热稳定性差和金属扩散污染。

公开(公告)号：US20090026516A1

公开(公告)日：2009-01-29

申请号：US11951270

申请日：2007-12-05

Applicant: Chien-Li CHENG ,  Shian-Jyh Lin ,  Ming-Yuan Huang

Inventor： Chien-Li CHENG ,  Shian-Jyh Lin ,  Ming-Yuan Huang

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10867

Abstract: A method for fabricating a semiconductor memory device. A pair of neighboring trench capacitors is formed in a substrate. An insulating layer having a pair of connecting structures therein is formed on the substrate, in which the pair of connecting structures is electrically connected to the pair of neighboring trench capacitors. An active layer is formed on the insulating layer between the pair of connecting structures so as to cover the pair of connecting structures. A pair of gate structures is formed on the active layer to electrically connect to the pair of trench capacitors. A semiconductor memory device is also disclosed.

Abstract translation: 一种制造半导体存储器件的方法。 在衬底中形成一对相邻的沟槽电容器。 在其上形成有一对连接结构的绝缘层，其中一对连接结构电连接到一对相邻的沟槽电容器。 在一对连接结构之间的绝缘层上形成有源层，以便覆盖该对连接结构。 在有源层上形成一对栅极结构，以电连接到该对沟槽电容器。 还公开了一种半导体存储器件。

公开(公告)号：US20090008692A1

公开(公告)日：2009-01-08

申请号：US11966891

申请日：2007-12-28

Applicant: Shian-Jyh Lin ,  Yu-Pi Lee ,  Ming-Yuan Huang ,  Jar-Ming Ho ,  Shun-Fu Chen ,  Tse-Chuan Kuo

Inventor： Shian-Jyh Lin ,  Yu-Pi Lee ,  Ming-Yuan Huang ,  Jar-Ming Ho ,  Shun-Fu Chen ,  Tse-Chuan Kuo

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10876 ,  H01L27/10894

Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate has a memory array region and a peripheral circuit region; a first active region and a second active region in the peripheral circuit region; a recessed gate disposed on the memory array region, comprising a first gate dielectric layer on the semiconductor substrate, wherein the first gate dielectric layer has a first thickness; and a second gate dielectric layer on the peripheral circuit region, wherein the second gate dielectric layer on the first active layer has a second thickness, and the second gate dielectric layer on the second active layer has a third thickness.

Abstract translation: 半导体器件包括半导体衬底。 半导体衬底具有存储器阵列区域和外围电路区域; 外围电路区域中的第一有源区和第二有源区; 设置在所述存储器阵列区域上的凹入栅极，包括在所述半导体衬底上的第一栅极介电层，其中所述第一栅极介电层具有第一厚度; 以及在所述外围电路区上的第二栅介质层，其中所述第一有源层上的所述第二栅介质层具有第二厚度，并且所述第二有源层上的所述第二栅介质层具有第三厚度。