公开(公告)号：US20080296701A1

公开(公告)日：2008-12-04

申请号：US11956633

申请日：2007-12-14

申请人： Tsung-Mu Lai ,  Shao-Chang Huang ,  Wen-hao Ching ,  Chun-Hung Lu ,  Shih-Chen Wang ,  Ming-Chou Ho

发明人： Tsung-Mu Lai ,  Shao-Chang Huang ,  Wen-hao Ching ,  Chun-Hung Lu ,  Shih-Chen Wang ,  Ming-Chou Ho

IPC分类号： H01L27/112

CPC分类号： H01L27/112 ,  G11C17/16 ,  G11C17/18 ,  H01L27/11206

摘要： A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a gate dielectric layer, a first gate and a second gate. The substrate is of a first conductive type. The first doped region and the second doped region are of a second conductive type and are separately disposed in the substrate. The gate dielectric layer is disposed on the substrate between the first doped region and the second doped region. The first gate and the second gate are disposed on the gate dielectric layer, respectively. The first gate is adjacent to the first doped region, while the second gate is adjacent to the second doped region. Here, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect.

摘要翻译： 一种包括衬底，第一掺杂区域，第二掺杂区域，栅极电介质层，第一栅极和第二栅极的可编程只读存储器（OTP-ROM）。 衬底是第一导电类型。 第一掺杂区域和第二掺杂区域是第二导电类型，并且分别设置在衬底中。 栅电介质层设置在第一掺杂区和第二掺杂区之间的衬底上。 第一栅极和第二栅极分别设置在栅极介电层上。 第一栅极与第一掺杂区相邻，而第二栅极与第二掺杂区相邻。 这里，第一个栅极电耦合接地，OTP-ROM通过击穿效应进行编程。

公开(公告)号：US20100006924A1

公开(公告)日：2010-01-14

申请号：US12171301

申请日：2008-07-11

申请人： Hsin-Ming Chen ,  Shao-Chang Huang ,  Shih-Chen Wang ,  Tsung-Mu Lai ,  Ming-Chou Ho ,  Chrong-Jung Lin

发明人： Hsin-Ming Chen ,  Shao-Chang Huang ,  Shih-Chen Wang ,  Tsung-Mu Lai ,  Ming-Chou Ho ,  Chrong-Jung Lin

IPC分类号： H01L27/112

CPC分类号： H01L27/112 ,  H01L27/11206 ,  H01L27/11521

摘要： A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a third doped region, a first dielectric layer, a select gate, a second dielectric layer, a first channel, a second channel and a silicide layer is provided. The first doped region, the second doped region and the third doped region are disposed apart in a substrate. The first dielectric layer is disposed on the substrate between the first doped region and the second doped region. The select gate is disposed on the first dielectric layer. The second dielectric layer is disposed on the substrate between the second doped region and the third doped region. The silicide layer is disposed on the first doped region, the second doped region and the third doped region. The OTP-ROM stores data by a punch-through effect occurring between the second doped region and the third doped region.

摘要翻译： 一种包括衬底，第一掺杂区域，第二掺杂区域，第三掺杂区域，第一介电层，选择栅极，第二介电层，第一沟道 ，提供第二通道和硅化物层。 第一掺杂区域，第二掺杂区域和第三掺杂区域设置在衬底中。 第一介电层设置在第一掺杂区和第二掺杂区之间的衬底上。 选择栅极设置在第一电介质层上。 第二介电层设置在第二掺杂区和第三掺杂区之间的衬底上。 硅化物层设置在第一掺杂区域，第二掺杂区域和第三掺杂区域上。 OTP-ROM通过发生在第二掺杂区域和第三掺杂区域之间的穿透效应来存储数据。

公开(公告)号：US06417046B1

公开(公告)日：2002-07-09

申请号：US09563834

申请日：2000-05-05

申请人： Ming-Chou Ho ,  Wen-Ting Chu ,  Chang Song Lin ,  Chuan-Li Chang ,  Hsin-Ming Chen ,  Di-Son Kuo

发明人： Ming-Chou Ho ,  Wen-Ting Chu ,  Chang Song Lin ,  Chuan-Li Chang ,  Hsin-Ming Chen ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L21/28211 ,  H01L21/28247 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/511 ,  H01L29/6659

摘要： A modified nitride spacer and making of the same are disclosed. The modified nitride spacer is formed adjacent a high-temperature oxide (HTO) layer which in turn is formed adjacent the sidewalls of a gate electrode. It is shown that the placement of an intervening oxide layer between the sidewalls of the gate electrode and the nitride spacer, in that order only, provides a significant improvement in charge retention in floating gate memory cells. Also, forming of the spacer from pure, undoped oxide only yields the same favorable results.

公开(公告)号：US06303454B1

公开(公告)日：2001-10-16

申请号：US09590849

申请日：2000-06-09

申请人： Juang-Ker Yeh ,  Jian-Hsing Lee ,  Kuo-Reay Peng ,  Ming-Chou Ho

发明人： Juang-Ker Yeh ,  Jian-Hsing Lee ,  Kuo-Reay Peng ,  Ming-Chou Ho

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  G11C16/14 ,  H01L21/28273 ,  H01L29/7885

摘要： The present invention provides method to fabricate a snap-back flash EEPROMS device. The method begins by forming a gate structure 22 24 28 26 on a substrate. The gate structure comprises: a tunnel oxide layer 22, a floating gate 24, integrate dielectric layer 28, and a control gate 26. A drain 14 is formed adjacent to the gate structure by an masking 51 and ion implant process. Next, a source side doped region 18 is formed adjacent to and under a portion of the gate structure 22 24 28 26 by an masking and ion implant process. Spacers 32 are now formed on the sidewalls of the gate structure. A source 20 is formed overlapping portion of the side source doped region 18 and adjacent to the spacers 32. The side source doped region has a lower dopant concentration than the source 20. This method forms a snap-back memory cell wherein the side source doped region 18 is used to apply a high voltage to operate the EEPROM cell in a snap-back erase mode.

摘要翻译： 本发明提供了制造快速闪存EEPROMS设备的方法。 该方法开始于在衬底上形成栅极结构22 24 28 26。 栅极结构包括：隧道氧化物层22，浮置栅极24，整合电介质层28和控制栅极26.漏极14通过掩模51和离子注入工艺邻近栅极结构形成。 接下来，通过掩模和离子注入工艺在栅极结构22 24 28 26的一部分附近形成源极侧掺杂区18。 隔板32现在形成在栅极结构的侧壁上。 源极20形成在侧面源极掺杂区域18的重叠部分并且与间隔物32相邻。源极掺杂区域具有比源极20更低的掺杂剂浓度。该方法形成一个回写式存储器单元，其中侧面源掺杂 区域18用于施加高电压以快速擦除模式操作EEPROM单元。

公开(公告)号：US5949717A

公开(公告)日：1999-09-07

申请号：US928217

申请日：1997-09-12

申请人： Ming-Chou Ho ,  Juang-ker Yeh ,  Jian-Hsing Lee ,  Kuo-Reay Peng

发明人： Ming-Chou Ho ,  Juang-ker Yeh ,  Jian-Hsing Lee ,  Kuo-Reay Peng

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C16/16

摘要： A method to erase data from a flash EEPROM cell while electrical charges trapped in the tunnel oxide of a flash EEPROM cell are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by first applying a first relatively high positive voltage pulse to the source of the flash EEPROM cell. Simultaneously a ground reference voltage is applied to the control gate and to the semiconductor substrate. At this same time the drain is floating. The flash EEPROM cell is then detrapped by floating the source and drain and applying a second relatively high positive voltage pulse to the semiconductor substrate. At the same time a relatively large negative voltage pulse is applied to the control gate.

摘要翻译： 在快速EEPROM单元的隧道氧化物中捕获电荷的同时消除闪存EEPROM单元中的数据的方法，以在扩展的编程和擦除周期之后保持编程的阈值电压和擦除的阈值电压的适当分离。 擦除快闪EEPROM单元的方法首先是将第一相对较高的正电压脉冲施加到闪速EEPROM单元的源。 同时，对控制栅极和半导体衬底施加接地参考电压。 在同一时间，排水沟漂浮。 然后通过漂浮源极和漏极并将第二相对高的正电压脉冲施加到半导体衬底来去除快闪EEPROM单元。 同时，向控制栅极施加相当大的负电压脉冲。

公开(公告)号：US6055183A

公开(公告)日：2000-04-25

申请号：US957678

申请日：1997-10-24

申请人： Ming-Chou Ho ,  Jian-Hsing Lee ,  Kuo-Reay Peng ,  Juang-Ke Yeh

发明人： Ming-Chou Ho ,  Jian-Hsing Lee ,  Kuo-Reay Peng ,  Juang-Ke Yeh

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C16/16

摘要： A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles, while preventing damage due to high field stress in the tunneling oxide. The method to erase a flash EEPROM cell begins by applying a relatively high positive voltage pulse to the source of the EEPROM cell. Simultaneously a ground reference voltage is applied to the drain and to the semiconductor substrate. At the same time a relatively large negative voltage pulse is applied to the control gate. This will cause a parasitic bipolar transistor to conduct and go into a snap back condition reducing the voltage field in the tunneling oxide.

摘要翻译： 在快速EEPROM的隧道氧化物中捕获电荷的同时消除闪存EEPROM中的数据的方法，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离，同时防止由于高 隧道氧化物中的场应力。 擦除快闪EEPROM单元的方法是通过向EEPROM单元的源极施加相对高的正电压脉冲开始的。 同时，对漏极和半导体衬底施加接地参考电压。 同时，向控制栅极施加相当大的负电压脉冲。 这将导致寄生双极晶体管导通并进入快速恢复条件，从而减少隧道氧化物中的电压场。

公开(公告)号：US5862078A

公开(公告)日：1999-01-19

申请号：US907984

申请日：1997-08-11

申请人： Juang-Ker Yeh ,  Jian-Hsing Lee ,  Kuo-Reay Peng ,  Ming-Chou Ho

发明人： Juang-Ker Yeh ,  Jian-Hsing Lee ,  Kuo-Reay Peng ,  Ming-Chou Ho

IPC分类号： G11C16/14 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/14 ,  G11C16/349

摘要： A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by channel erasing to detrap the tunneling oxide of the flash EEPROM cell. The channel erasing consists floating the drain and the second diffusion well and concurrently applying the ground reference potential to the semiconductor substrate and the first diffusion well. Concurrently a first relatively large negative voltage pulse is applied to the control gate, as a first moderately large positive voltage pulse is applied to said source. The method to erase then proceeds with the source erasing to remove charges from the floating gate of the flash EEPROM cell. The source erasing consists of applying a second relatively large negative voltage pulse to the control gate of said EEPROM cell and concurrently applying a second moderately large positive voltage pulse to a first diffusion well. At the same time the ground reference potential continues to be applied to the semiconductor substrate, while the drain and a second diffusion well is allowed to float.

摘要翻译： 一种在闪存EEPROM的隧穿氧化物中捕获电荷的情况下从闪存EEPROM擦除数据的方法被消除，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离。 擦除快闪EEPROM单元的方法是通过通道擦除来消除快速EEPROM单元的隧道氧化物。 通道擦除包括使漏极和第二扩散阱浮置，同时将接地参考电位施加到半导体衬底和第一扩散阱。 同时，第一相对较大的负电压脉冲施加到控制栅极，因为第一适度大的正电压脉冲被施加到所述源极。 擦除方法随后进行源擦除以从快闪EEPROM单元的浮动栅极去除电荷。 源擦除包括将第二相对较大的负电压脉冲施加到所述EEPROM单元的控制栅并且向第一扩散阱同时施加第二适度大的正电压脉冲。 同时，接地参考电位继续施加到半导体衬底，同时漏极和第二扩散阱被允许浮动。

公开(公告)号：US6049484A

公开(公告)日：2000-04-11

申请号：US150907

申请日：1998-09-10

申请人： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Juang-Ke Yeh ,  Ming-Chou Ho

发明人： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Juang-Ke Yeh ,  Ming-Chou Ho

IPC分类号： G11C16/14 ,  G11C16/04

CPC分类号： G11C16/14

摘要： A method to erase data from a flash EEPROM is disclosed. Electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by erasing the flash EEPROM cell by first applying a high positive voltage pulse to the source of the EEPROM cell. Simultaneously, a ground reference potential is applied to the semiconductor substrate and the control gate. At this same time the drain is floating. Floating the source and drain and applying the ground reference potential to the semiconductor substrate then detraps the flash EEPROM cell. At the same time, a relatively large negative voltage pulse is applied to the control gate.

摘要翻译： 公开了一种从闪存EEPROM擦除数据的方法。 消除了捕获在闪速EEPROM的隧穿氧化物中的电荷，以在扩展编程和擦除周期之后保持编程的阈值电压和擦除的阈值电压的适当分离。 通过首先向EEPROM单元的源施加高正电压脉冲，擦除快闪EEPROM单元开始擦除快闪EEPROM单元的方法。 同时，对半导体衬底和控制栅极施加接地参考电位。 在同一时间，排水沟漂浮。 将源极和漏极浮置并将接地参考电位施加到半导体衬底，然后去除快闪EEPROM单元。 同时，向控制栅极施加相对较大的负电压脉冲。

公开(公告)号：US5726933A

公开(公告)日：1998-03-10

申请号：US857162

申请日：1997-05-15

申请人： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Juang-Ke Yeh ,  Ming-Chou Ho

发明人： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Juang-Ke Yeh ,  Ming-Chou Ho

IPC分类号： G11C16/10 ,  G11C16/14 ,  G11C16/06

CPC分类号： G11C16/14 ,  G11C16/10

摘要： The present invention provides method to erase and program flash EEPROMS devices using a clipped sine waveform (Vg). The clipped sine waveform reduces the tunneling oxide electric field between the floating gate and the source or drain region thereby reducing electron trapping. The method for the erase cycle comprises: applying a positive voltage to a source region; grounding a well region; floating the drain region; and simultaneously applying a negative clipped sine waveform voltage to a control gate during the erase cycle. The program cycle of the invention comprises: applying a voltage to a drain region; grounding a well region; floating a source region; and simultaneously applying a clipped sine waveform voltage to the control gate whereby the clipped sine waveforms reduce the electric field in a tunnel oxide layer which reduces the electron trapping.

摘要翻译： 本发明提供了使用限幅正弦波形（Vg）擦除和编程闪存EEPROMS设备的方法。 限幅正弦波形减少了浮动栅极和源极或漏极区域之间的隧道氧化物电场，从而减少了电子俘获。 擦除周期的方法包括：向源极区域施加正电压; 接地井区; 漂浮漏极区; 并且在擦除周期期间同时向控制栅极施加负的限幅正弦波形电压。 本发明的程序循环包括：向漏区施加电压; 接地井区; 浮动源区; 并且同时向限制栅极施加限幅正弦波形电压，由此限幅正弦波形减少隧道氧化物层中的电场，从而减少电子捕获。

公开(公告)号：US6117732A

公开(公告)日：2000-09-12

申请号：US193671

申请日：1998-11-17

申请人： Wen-Ting Chu ,  Chuan-Li Chang ,  Ming-Chou Ho ,  Chang-Song Lin ,  Di-Son Kuo

发明人： Wen-Ting Chu ,  Chuan-Li Chang ,  Ming-Chou Ho ,  Chang-Song Lin ,  Di-Son Kuo

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A method for fabricating a single polysilicon, non-volatile memory device, has been developed. The method features the use of a metal structure, comprised to contact an underlying control gate region, located in the semiconductor structure, in addition to providing the upper electrode, for a capacitor structure. The capacitor structure, in addition to the metal structure used as the upper electrode, is also comprised of an underlying capacitor dielectric layer, and an underlying polysilicon floating gate structure, used as the lower electrode of the capacitor structure. The creation of the capacitor structure results in performance increases realized via the additional control gate coupling capacitance, obtained via the novel configuration described in this invention.

摘要翻译： 已经开发了用于制造单个多晶硅，非易失性存储器件的方法。 该方法的特征在于，除了为电容器结构提供上电极之外，金属结构的使用还包括接触位于半导体结构中的底层控制栅极区域。 除了用作上电极的金属结构之外，电容器结构还包括用作电容器结构的下电极的下层电容器介电层和下面的多晶硅浮栅结构。 电容器结构的产生导致通过经由本发明中描述的新颖结构获得的附加控制栅极耦合电容实现的性能提高。