公开(公告)号：US20110255323A1

公开(公告)日：2011-10-20

申请号：US12977243

申请日：2010-12-23

申请人： Kanji Otsuka ,  Tsuneo Ito ,  Yoichi Sato ,  Masahiro Yoshida ,  Shigeru Yamamoto ,  Takeshi Koyama ,  Yuko Tanba ,  Yutaka Akiyama

发明人： Kanji Otsuka ,  Tsuneo Ito ,  Yoichi Sato ,  Masahiro Yoshida ,  Shigeru Yamamoto ,  Takeshi Koyama ,  Yuko Tanba ,  Yutaka Akiyama

IPC分类号： G11C5/06

CPC分类号： G06F13/4022 ,  G11C5/02 ,  G11C7/1006 ,  G11C2213/71

摘要： There is a problem that a bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. In an example of a memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memories 20 including basic cells 10 arranged in a cluster, the basic cell 10 including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories 20 located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus 11 including a through-via, an arbitrary one of the basic cells 10 is directly accessed through the multibus 11 from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell 10 is switched to a logic circuit as conjugate.

摘要翻译： 存在带宽瓶颈的问题，因为使用交叉开关来应对规模的增加。 在根据本发明的存储器/逻辑共轭系统的示例中，多个集群存储器芯片，每个集群存储器芯片包括多个集群存储器20，其包括布置在集群中的基本单元10，基本单元10包括存储器电路，以及 控制多个集群存储器的控制器芯片是三维堆叠的，沿着多个集群存储器芯片的堆叠方向定位的多个集群存储器20和控制器芯片经由多片11电连接到控制器芯片， 通孔中，任意一个基本单元10通过多轴11从控制器芯片直接访问，从而将真值数据写入其中，从而将任意的基本单元10切换到逻辑电路作为共轭。

公开(公告)号：US07791852B2

公开(公告)日：2010-09-07

申请号：US11819579

申请日：2007-06-28

申请人： Kanji Otsuka ,  Tamotsu Usami ,  Yutaka Akiyama ,  Tsuneo Ito ,  Yuko Tanba

发明人： Kanji Otsuka ,  Tamotsu Usami ,  Yutaka Akiyama ,  Tsuneo Ito ,  Yuko Tanba

IPC分类号： H02H3/22

CPC分类号： H01L27/0266

摘要： Disclosed is an electrostatic discharge protection circuit capable of realizing speeding up of differential signals by reducing a capacitance of the circuit. Transmission lines are connected to an IN terminal and an IN Bar terminal and differential signals are input to the terminals. The ESD protection circuit is connected to the transmission lines and protects an internal circuit from a surge voltage applied to the IN terminal and the IN Bar terminal. A pair of transistors of the ESD protection circuit is formed in the same well. Thereby, when differential signals transit, charges in drains of the pair of transistors holding a state before a transition transfer in the same well. As a result, the capacitances in the drains of the pair of transistors are reduced with respect to the transition of differential signals so that the speeding up of differential signals can be realized.

摘要翻译： 公开了一种能够通过减小电路的电容来实现差分信号的加速的静电放电保护电路。 传输线连接到IN端子，IN条形端子和差分信号输入端子。 ESD保护电路连接到传输线，并保护内部电路免受施加到IN端子和IN Bar端子的浪涌电压。 ESD保护电路的一对晶体管形成在同一个阱中。 因此，当差分信号转移时，在同一井内转移转移之前保持状态的一对晶体管的漏极中的电荷。 结果，一对晶体管的漏极中的电容相对于差分信号的转变而减小，从而可以实现差分信号的加速。

公开(公告)号：US4928550A

公开(公告)日：1990-05-29

申请号：US254638

申请日：1988-10-07

申请人： Takeshi Sakai ,  Tsuneo Ito

发明人： Takeshi Sakai ,  Tsuneo Ito

IPC分类号： F16C3/14 ,  F16C9/02

CPC分类号： F16H57/043 ,  F16C3/14 ,  F16C9/02 ,  F16H57/0469 ,  F16C3/08 ,  Y10T74/2173 ,  Y10T74/2175

摘要： A sliding bearing and a crankshaft used for a crankshaft-connecting rod assembly are disclosed. Particularly, the invention concerns a sliding bearing for a crankshaft-connecting rod assembly, in which journal sections are each provided at each end of at least one crankshaft, one of said journal sections is rotatably supported so that said crankshaft is rotated about said one journal section, a connecting rod has one end rotatably coupled to said other journal section, and a lubricant is supplied form an oil port of each said journal section. The bearing surface of a cylindrical sliding bearing for supporting one of the journal sections with a predetermined clearance or the bearing surface of a cylindrical sliding bearing provided with a predetermined clearance between the other journal section and a connecting rod is formed with a recess, preferably a shallow recess, which corresponds in position to the oil port of each journal section, from which the lubricant is supplied or caused to flow, and extending in the circumferential direction of the sliding bearing. The invention further concerns a crankshaft, in which the outer periphery of at least one of the journal sections of the crankshaft is formed with a recess including the oil port extending in the circumferential direction of the journal section.

摘要翻译： 公开了一种用于曲轴连杆组件的滑动轴承和曲轴。 特别地，本发明涉及一种用于曲轴连杆组件的滑动轴承，其中轴颈部分各自设置在至少一个曲轴的每个端部，所述轴颈部分中的一个被可旋转地支撑，使得所述曲轴围绕所述一个轴颈旋转 连杆具有可旋转地联接到所述另一个轴颈部分的一端，并且从每个所述轴颈部分的油口供应润滑剂。 用于以预定间隙支撑轴颈部分之一的圆柱形滑动轴承的轴承表面或在另一轴颈部分和连杆之间设置有预定间隙的圆柱形滑动轴承的支承表面形成有凹部，优选为 浅凹槽，其位于每个轴颈部分的油口处，供应润滑剂或使其流动，并在滑动轴承的圆周方向上延伸。 本发明还涉及一种曲轴，其中曲轴的轴颈部分的至少一个的外周形成有包括在轴颈部分的圆周方向上延伸的油口的凹部。

公开(公告)号：US4085458A

公开(公告)日：1978-04-18

申请号：US690303

申请日：1976-05-26

申请人： Kunihiko Ikuzaki ,  Tsuneo Ito ,  Masamichi Ishihara ,  Takashi Sato

发明人： Kunihiko Ikuzaki ,  Tsuneo Ito ,  Masamichi Ishihara ,  Takashi Sato

IPC分类号： G11C11/407 ,  G11C7/02 ,  G11C11/405

CPC分类号： G11C11/405

摘要： In a n-channel (or p-channel) random access memory in which a plurality of memory cells are arranged in a matrix form in a p-type (or n-type) semiconductor substrate, clamping MOSFET's are connected between word lines provided for the associated rows of memory cells of the matrix and a reference potential to which gates the source electrodes of the information storing MOSFET's of the memory cells are connected. The clamping MOSFET has a lower threshold voltage than a row selecting MOSFET connected to the word line and clamps the word line when the word line is not selected, so that a delay in the read-out operation is eliminated or suppressed.

摘要翻译： 在p沟道（或p沟道）随机存取存储器中，多个存储单元以矩阵形式布置在p型（或n型）半导体衬底中，钳位MOSFET连接在用于 矩阵的相关行的存储单元和存储单元的存储MOSFET的信息的源电极的栅极的参考电位。 钳位MOSFET具有比连接到字线的行选择MOSFET低的阈值电压，并且当未选择字线时钳位字线，从而消除或抑制读出操作的延迟。

公开(公告)号：US3980899A

公开(公告)日：1976-09-14

申请号：US547494

申请日：1975-02-06

申请人： Shunji Shimada ,  Tsuneo Ito

发明人： Shunji Shimada ,  Tsuneo Ito

IPC分类号： G11C11/41 ,  G11C11/407 ,  G11C11/413 ,  G11C11/418 ,  H03K17/687 ,  H03K19/0185 ,  H03K5/18 ,  G11C7/00 ,  H03K3/353

CPC分类号： H03K19/018507 ,  G11C11/418

摘要： For driving a plurality of memory cells, a driver circuit, connected to the word driver line of the memory cells, includes a resistive connection, connected between the word line and ground potential, for preventing the potential of the word line from floating. The driver circuit includes an enhancement-type switching MOSFET and a depletion type resistor MOSFET connected in series. By virtue of the connection of a gate of the depletion type MOSFET, the depletion type MOSFET is always turned on so that whether or not the switching type enhancement MOSFET is turned on, the common connection between the switching MOSFET and the resistive MOSFET will always be at a prescribed potential thereby preventing the word driver line from floating.

摘要翻译： 为了驱动多个存储单元，连接到存储器单元的字驱动器线的驱动电路包括连接在字线和地电位之间的电阻连接，用于防止字线浮动。 驱动器电路包括串联连接的增强型开关MOSFET和耗尽型电阻MOSFET。 由于耗尽型MOSFET的栅极的连接，耗尽型MOSFET总是导通，使得开关型增强MOSFET是否导通，开关MOSFET和电阻MOSFET之间的共同连接将始终为 从而防止字驱动器线漂浮。