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公开(公告)号：US4085458A
公开(公告)日：1978-04-18
申请号：US690303
申请日：1976-05-26
申请人： Kunihiko Ikuzaki , Tsuneo Ito , Masamichi Ishihara , Takashi Sato
发明人： Kunihiko Ikuzaki , Tsuneo Ito , Masamichi Ishihara , Takashi Sato
IPC分类号： G11C11/407 , G11C7/02 , G11C11/405
CPC分类号： G11C11/405
摘要： In a n-channel (or p-channel) random access memory in which a plurality of memory cells are arranged in a matrix form in a p-type (or n-type) semiconductor substrate, clamping MOSFET's are connected between word lines provided for the associated rows of memory cells of the matrix and a reference potential to which gates the source electrodes of the information storing MOSFET's of the memory cells are connected. The clamping MOSFET has a lower threshold voltage than a row selecting MOSFET connected to the word line and clamps the word line when the word line is not selected, so that a delay in the read-out operation is eliminated or suppressed.
摘要翻译： 在p沟道（或p沟道）随机存取存储器中，多个存储单元以矩阵形式布置在p型（或n型）半导体衬底中，钳位MOSFET连接在用于 矩阵的相关行的存储单元和存储单元的存储MOSFET的信息的源电极的栅极的参考电位。 钳位MOSFET具有比连接到字线的行选择MOSFET低的阈值电压，并且当未选择字线时钳位字线，从而消除或抑制读出操作的延迟。
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2.发明授权公开(公告)号：US08344356B2
公开(公告)日：2013-01-01
申请号：US12735259
申请日：2008-12-17
申请人： Ryo Sakamoto , Jo Shimizu , Tsuneo Ito , Takashi Egawa
发明人： Ryo Sakamoto , Jo Shimizu , Tsuneo Ito , Takashi Egawa
IPC分类号： H01L296/06
CPC分类号： H01L29/155 , H01L21/02381 , H01L21/02458 , H01L21/02507 , H01L21/0251 , H01L21/0254 , H01L29/2003 , H01L33/007 , H01L33/04 , H01L33/12
摘要： A semiconductor material is provided comprising: a composition graded layer, formed on a Si substrate or an interlayer formed thereon, comprising a composition of AlXGa1-XN graded such that a content ratio of Al in the composition decreases continuously or discontinuously in a crystal growing direction; a superlattice composite layer, formed on the composition graded layer, comprising a high Al-containing layer comprising a composition of AlYGa1-YN and a low Al-containing layer comprising a composition of AlZGa1-ZN that are laminated alternately; and a nitride semiconductor layer formed on the superlattice composite layer.
摘要翻译： 提供了一种半导体材料，包括：在Si衬底或其上形成的中间层上形成的组成分级层，其包含AlXGa1-XN的组成，其分级使得组合物中Al的含量比在晶体生长方向上连续地或不连续地降低 ; 在组成梯度层上形成的超晶格复合层，包括含有AlYGa1-YN组成的高含Al层和交替叠层的包含AlZGa1-ZN组成的低含Al层; 以及形成在超晶格复合层上的氮化物半导体层。
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公开(公告)号：US4502430A
公开(公告)日：1985-03-05
申请号：US549327
申请日：1983-11-07
申请人： Shinichi Yokoi , Tsuneo Ito
发明人： Shinichi Yokoi , Tsuneo Ito
CPC分类号： F23Q7/001 , H05B3/48 , F23Q2007/004 , H05B2203/027
摘要： A ceramic heater including a ceramic insulator having a circular cross section, and a heating coil having an oval cross section, embedded in the insulator along the length thereof, and bent in a U-shaped form with the bend adjacent one end of the insulator. One of a pair of parallel coil portions defining the U-shaped coil has a long cross sectional diameter lying parallel to that of the other coil portion. The diameter of a cylinder defined by the outer surfaces of the coil portions and the outside diameter of the insulator have a ratio of 35:100 to 70:100.
摘要翻译： 一种陶瓷加热器，包括具有圆形截面的陶瓷绝缘体和具有椭圆形横截面的加热线圈，其沿着其长度嵌入绝缘体中，并且弯曲成U形形状，邻近绝缘体的一端附近的弯曲。 限定U形线圈的一对平行线圈部分中的一个具有平行于另一个线圈部分的长横截面直径。 由线圈部分的外表面限定的圆柱体的直径和绝缘体的外径的比率为35:100至70:100。
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公开(公告)号：US4195988A
公开(公告)日：1980-04-01
申请号：US943497
申请日：1978-09-18
申请人： Tsuneo Ito
发明人： Tsuneo Ito
摘要： An alloy for spark plug center electrodes comprising about 1 to about 10% by weight of chromium, about 30 to about 70% by weight of palladium and the balance gold.
摘要翻译： 一种用于火花塞中心电极的合金，其包括约1至约10重量％的铬，约30至约70重量％的钯和余量的金。
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5.发明申请公开(公告)号：US20110001127A1
公开(公告)日：2011-01-06
申请号：US12735259
申请日：2008-12-17
申请人： Ryo Sakamoto , Jo Shimizu , Tsuneo Ito , Takashi Egawa
发明人： Ryo Sakamoto , Jo Shimizu , Tsuneo Ito , Takashi Egawa
CPC分类号： H01L29/155 , H01L21/02381 , H01L21/02458 , H01L21/02507 , H01L21/0251 , H01L21/0254 , H01L29/2003 , H01L33/007 , H01L33/04 , H01L33/12
摘要： A semiconductor material is provided comprising: a composition graded layer, formed on a Si substrate or an interlayer formed thereon, comprising a composition of AlXGa1-XN graded such that a content ratio of Al in the composition decreases continuously or discontinuously in a crystal growing direction; a superlattice composite layer, formed on the composition graded layer, comprising a high Al-containing layer comprising a composition of AlYGa1-YN and a low Al-containing layer comprising a composition of AlZGa1-ZN that are laminated alternately; and a nitride semiconductor layer formed on the superlattice composite layer.
摘要翻译： 提供了一种半导体材料，包括：在Si衬底或其上形成的中间层上形成的组成分级层，其包含AlXGa1-XN的组成，其分级使得组合物中Al的含量比在晶体生长方向上连续地或不连续地降低 ; 在组成梯度层上形成的超晶格复合层，包括含有AlYGa1-YN组成的高含Al层和交替叠层的包含AlZGa1-ZN组成的低含Al层; 以及形成在超晶格复合层上的氮化物半导体层。
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公开(公告)号：US5844369A
公开(公告)日：1998-12-01
申请号：US855916
申请日：1997-05-14
申请人： Yuji Yoshizako , Tsuneo Ito , Akie Nakamoto
发明人： Yuji Yoshizako , Tsuneo Ito , Akie Nakamoto
CPC分类号： H05H1/46
摘要： A phase adjusting circuit for adjusting phases of output powers from two high frequency power generators in a plasma processing apparatus comprises first and second synthesizing circuits for generating first and second high frequency signals of a predetermined waveform with frequencies of f0 and f0.+-..DELTA.f (.DELTA.f
摘要翻译： 用于调整等离子体处理装置中的两个高频发电机的输出功率的相位的相位调整电路包括用于产生频率为f0和f0 +/- DELTA f的预定波形的第一和第二高频信号的第一和第二合成电路（ DELTA f << f0），用于检测板电极的检测信号之间的相位差的相位差检测电路，用于产生具有与确定的相位相同的第一频率信号的频率和波形的高频信号的第三波形合成电路 来自相位差和相位差检测电路的输出之间的相位误差，以及基于第一和第三波形合成电路的输出确定两个高频发电机的输出功率的相位调整电路。
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公开(公告)号：US4833474A
公开(公告)日：1989-05-23
申请号：US88418
申请日：1987-08-24
IPC分类号： H03M3/04
摘要： An A/D converter apparatus comprises: a sampling signal generating means to generate an oversampling signal and an internal sampling signal; a converter means to convert an input analog signal into a digital signal in synchronism with the oversampling signal; and a decimator means to perform a specified decimation on the digital signal in synchronism with the internal sampling signal; whereby the sampling signal generating means maintains the frequencies of the oversampling signal and the internal sampling signal in a specified relationship.
摘要翻译： A / D转换装置包括：采样信号发生装置，用于产生过采样信号和内部采样信号; 转换器装置，用于将输入模拟信号转换成与过采样信号同步的数字信号; 以及抽取器装置，用于与内部采样信号同步地对数字信号执行指定的抽取; 由此采样信号发生装置以特定的关系维持过采样信号和内部采样信号的频率。
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公开(公告)号：US4272832A
公开(公告)日：1981-06-09
申请号：US41553
申请日：1979-05-23
申请人： Tsuneo Ito
发明人： Tsuneo Ito
IPC分类号： G11C11/41 , G11C11/417 , G11C7/00
CPC分类号： G11C11/417
摘要： A semiconductor memory device comprises an input address buffer circuit and a memory cell circuit which are constructed of static logic circuits, an address decoder circuit which is constructed of a dynamic logic circuit, a detector circuit which detects a change in an input address signal, and a pulse generator circuit which is started operating by an output signal of the detector circuit and which provides a clock signal for the dynamic logic circuit. Owing to the detector circuit and the pulse generator circuit, the semiconductor memory device operates without the necessity for any external clock signal.
摘要翻译： 一种半导体存储器件包括由静态逻辑电路构成的输入地址缓冲电路和存储单元电路，由动态逻辑电路构成的地址解码器电路，检测输入地址信号的变化的检测电路，以及 脉冲发生器电路通过检测器电路的输出信号开始工作，并为动态逻辑电路提供时钟信号。 由于检测器电路和脉冲发生器电路，半导体存储器件在不需要任何外部时钟信号的情况下工作。
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公开(公告)号：US4103406A
公开(公告)日：1978-08-01
申请号：US778099
申请日：1977-03-16
申请人： Tsuneo Ito , Tatuya Hashiba , Takesi Inoue , Kunihiro Nagata
发明人： Tsuneo Ito , Tatuya Hashiba , Takesi Inoue , Kunihiro Nagata
摘要： A split type sectional forming roll in which a split roll is formed at least two roll segments, a separating line of a roll segment to have an acute angle in a roll segment section adjacent to a side portion of another roll segment has an angle to a vertical line which is perpendicular to a roll shaft in outer peripheral portion and a separating line parallel to the above described vertical line in inner peripheral portion.Thereby the roll segments prevents damages of roll such as breakage or chipping out so that this split type sectional forming roll has a longer life sharply.
摘要翻译： 一种分割型断面成形辊，其中分割辊形成有至少两个辊段，在与另一个辊段的侧部相邻的辊段部分中具有锐角的辊段的分离线具有与 与外周部的辊轴垂直的垂直线和与内周部的上述垂直线平行的分离线。
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10.发明授权公开(公告)号：US08426893B2
公开(公告)日：2013-04-23
申请号：US13319910
申请日：2010-05-10
申请人： Tetsuya Ikuta , Jo Shimizu , Tomohiko Shibata , Ryo Sakamoto , Tsuneo Ito
发明人： Tetsuya Ikuta , Jo Shimizu , Tomohiko Shibata , Ryo Sakamoto , Tsuneo Ito
IPC分类号： H01L31/00
CPC分类号： H01L29/207 , H01L21/02378 , H01L21/02458 , H01L21/02488 , H01L21/02507 , H01L21/0254 , H01L29/1075 , H01L29/155 , H01L29/2003 , H01L29/7786
摘要： An epitaxial substrate for electronic devices is provided, which can improve vertical breakdown voltage and provides a method of producing the same. The epitaxial substrate includes a conductive SiC single crystal substrate, a buffer as an insulating layer on the SiC single crystal substrate, and a main laminate formed by epitaxially growing a plurality of Group III nitride layers on the buffer. Further, the buffer includes at least an initial growth layer in contact with the SiC single crystal substrate and a superlattice laminate having a superlattice multi-layer structure on the initial growth layer. The initial growth layer is made of a Ba1Alb1Gac1Ind1N material. Furthermore, the superlattice laminate is configured by alternately stacking a first layer made of a Ba2Alb2Gac2Ind2N material and a second layer made of a Ba3Alb3Gac3Ind3N material having a different band gap from the first layer.
摘要翻译： 提供了一种用于电子器件的外延衬底，其可以提高垂直击穿电压并提供其制造方法。 外延衬底包括导电SiC单晶衬底，在SiC单晶衬底上作为绝缘层的缓冲器，以及通过在缓冲器上外延生长多个III族氮化物层而形成的主叠层。 此外，缓冲器至少包括与SiC单晶衬底接触的初始生长层和在初始生长层上具有超晶格多层结构的超晶格层压体。 初始生长层由Ba1Alb1Gac1Ind1N材料制成。 此外，超晶格层叠体通过交替堆叠由Ba2Alb2Gac2Ind2N材料制成的第一层和由与第一层具有不同带隙的Ba3Alb3Gac3Ind3N材料制成的第二层而构成。
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