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公开(公告)号：US08023312B2
公开(公告)日：2011-09-20
申请号：US12515286
申请日：2007-11-05
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/003 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72 , G11C2213/76 , G11C2213/77 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1633
摘要： A nonvolatile semiconductor memory device include: a two terminal structured variable resistive element, wherein resistive characteristics defined by current-voltage characteristics at both ends transit between low and high resistance states stably by applying a voltage satisfying predetermined conditions to the both ends. A transition from the low resistance state to the high resistance state occurs by applying a voltage of a first polarity whose absolute value is at or higher than first threshold voltage, and the reverse transition occurs by applying a voltage of a second polarity whose absolute value is at or higher than a second threshold voltage. A load circuit is connected to the variable resistive element in series having an adjustable load resistance. A voltage generation circuit applies a voltage to both ends of a serial circuit. The variable resistive element can transit between the states by adjusting a resistance of the load circuit.
摘要翻译： 非易失性半导体存储器件包括：二端结构可变电阻元件，其中由两端的电流 - 电压特性限定的电阻特性通过向两端施加满足预定条件的电压来稳定地传递低电阻状态和高电阻状态。 通过施加绝对值等于或高于第一阈值电压的第一极性的电压而发生从低电阻状态向高电阻状态的转变，并且通过施加绝对值为绝对值的第二极性的电压， 等于或高于第二阈值电压。 负载电路与可变负载电阻串联连接到可变电阻元件。 电压产生电路向串联电路的两端施加电压。 可变电阻元件可以通过调整负载电路的电阻在状态之间转换。
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22.发明授权Variable resistive element, manufacturing method for same, and non-volatile semiconductor memory device 有权可变电阻元件，相同的制造方法和非易失性半导体存储器件公开(公告)号：US08054674B2
公开(公告)日：2011-11-08
申请号：US12598642
申请日：2008-04-07
申请人： Yukio Tamai , Yasunari Hosoi , Nobuyoshi Awaya , Shigeo Ohnishi , Kazuya Ishihara , Hisashi Shima , Hiroyuki Akinaga , Fumiyoshi Takano
发明人： Yukio Tamai , Yasunari Hosoi , Nobuyoshi Awaya , Shigeo Ohnishi , Kazuya Ishihara , Hisashi Shima , Hiroyuki Akinaga , Fumiyoshi Takano
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C11/5614 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/51 , G11C2213/56 , G11C2213/77 , H01L27/101 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： Provided is a variable resistive element which performs high speed and low power consumption operation. The variable resistive element comprises a metal oxide layer between first and second electrodes wherein electrical resistance between the first and second electrodes reversibly changes in accordance with application of electrical stress across the first and second electrodes. The metal oxide layer has a filament, which is a current path where the density of a current flowing between the first and second electrodes locally increases. A portion including at least the vicinity of an interface between the certain electrode, which is one or both of the first and second electrodes, and the filament, on an interface between the certain electrode and the metal oxide layer is provided with an interface oxide which is an oxide of at least one element included in the certain electrode and different from the oxide of the metal oxide layer.
摘要翻译： 提供一种执行高速和低功耗操作的可变电阻元件。 可变电阻元件包括在第一和第二电极之间的金属氧化物层，其中第一和第二电极之间的电阻根据跨越第一和第二电极的电应力的应用而可逆地改变。 金属氧化物层具有灯丝，其是在第一和第二电极之间流动的电流的密度局部增加的电流路径。 在特定电极和金属氧化物层之间的界面上至少包括作为第一和第二电极中的一个或两个的特定电极和灯丝之间的界面附近的部分设置有界面氧化物，其界面氧化物 是包含在该特定电极中并且与金属氧化物层的氧化物不同的至少一种元素的氧化物。
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公开(公告)号：US08036017B2
公开(公告)日：2011-10-11
申请号：US12563349
申请日：2009-09-21
申请人： Nobuyoshi Awaya , Takashi Nakano
发明人： Nobuyoshi Awaya , Takashi Nakano
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/005 , G11C13/0004 , G11C13/0011 , G11C13/0033 , G11C14/00 , G11C14/0045 , G11C2211/4016 , G11C2213/31 , H01L27/2436 , H01L27/2454 , H01L27/2472 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/146
摘要： An inexpensive nonvolatile memory having high performance which makes random write and readout possible an unlimited number of times is provided. A unit memory cell is formed of a MISFET having a channel body that is electrically isolated from a semiconductor substrate and a resistance change element having a two-terminal structure with one end electrically connected to a drain of the MISFET. The MISFET functions as a volatile memory element, and the resistance change element functions as a nonvolatile memory element, so that information stored in the MISFET is copied to the resistance change element before the power is turned OFF and information stored in the resistance change element is transferred to the MISFET when the power is turned ON, and thus, the MISFET is used as a volatile memory which makes random write and readout possible.
摘要翻译： 提供了具有高性能的便宜的非易失性存储器，其使得随机写入和读出可能无限次。 单元存储单元由具有与半导体基板电隔离的沟道体的MISFET和具有与MISFET的漏极电连接的一端的两端结构的电阻变化元件形成。 MISFET用作易失性存储元件，并且电阻变化元件用作非易失性存储元件，使得存储在MISFET中的信息在电源断开之前被复制到电阻变化元件，并且存储在电阻变化元件中的信息是 当电源接通时转移到MISFET，因此，MISFET被用作使随机写入和读出成为可能的易失性存储器。
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公开(公告)号：US06956280B2
公开(公告)日：2005-10-18
申请号：US10397090
申请日：2003-03-25
申请人： Masayuki Tajiri , Nobuyoshi Awaya
发明人： Masayuki Tajiri , Nobuyoshi Awaya
CPC分类号： G11C13/0007 , G06N3/063 , G11C11/54 , G11C2213/31
摘要： Input signals are weighted by weighting means composed of variable resistors, each made of an oxide thin film with a perovskite structure containing manganese, which changes resistance at room temperature according to the cumulative number of times a pulse voltage was applied and holds the resistance in a nonvolatile manner. Then, the weighted signals are inputted to an arithmetic unit. The oxide thin film used as each of the variable resistors changes its resistance, according to the cumulative number of times the input pulse was applied, and further holds the resistance in a nonvolatile manner even after the power supply is cut off. Thus, by changing the weighting factor according to the cumulative number of times the pulse voltage was applied, a neuro element more resembling a neuron of the human being is realized.
摘要翻译： 输入信号通过由可变电阻器组成的加权装置加权，每个可变电阻器由具有包含锰的钙钛矿结构的氧化物薄膜制成，其根据施加脉冲电压的累积次数在室温下改变电阻并且将电阻保持在 非挥发性。 然后，加权信号被输入到运算单元。 用作各可变电阻器的氧化物薄膜根据施加输入脉冲的累积次数而改变其电阻，并且即使在电源被切断之后也进一步保持电阻以非易失性方式。 因此，通过根据施加脉冲电压的累积次数来改变加权因子，实现了更类似于人的神经元的神经元素。
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公开(公告)号：US06711049B1
公开(公告)日：2004-03-23
申请号：US10282985
申请日：2002-10-28
申请人： Sheng Teng Hsu , Jong-Jan Lee , Fengyan Zhang , Nobuyoshi Awaya
发明人： Sheng Teng Hsu , Jong-Jan Lee , Fengyan Zhang , Nobuyoshi Awaya
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A one-transistor FeRAM memory cell array includes an array of ferroelectric transistors arranged in rows and columns, each transistor having a source, a drain, a channel, a gate oxide layer over the channel and a ferroelectric stack formed on the gate oxide layer; word lines connecting the gate ferroelectric stack top electrodes of transistors in a row of the array; a connection to the channel of all transistors in the array formed by a substrate well; a set of first bit lines connecting the sources of all transistors in a column of the array; and a set of second bit lines connecting the drains of all transistors in a column of the array; wherein the ferroelectric stack has opposed edges, which, when projected to a level of the source, drain and channel, are coincident with an abutted edge of the source and the channel and the drain and the channel, respectively.
摘要翻译： 单晶体管FeRAM存储单元阵列包括以行和列布置的铁电晶体管阵列，每个晶体管具有源极，漏极，沟道，沟道上的栅极氧化物层和形成在栅极氧化物层上的铁电堆叠; 连接阵列中的晶体管的栅极铁电叠层顶部电极的字线; 连接到由衬底阱形成的阵列中的所有晶体管的沟道; 连接阵列的列中的所有晶体管的源的一组第一位线; 以及连接阵列中的所有晶体管的漏极的一组第二位线; 其中所述铁电堆叠具有相对的边缘，当所述铁电堆叠被投影到所述源极的水平面时，所述漏极和沟道分别与所述源极和所述沟道以及所述漏极和所述沟道的邻接边缘重合。
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公开(公告)号：US07535746B2
公开(公告)日：2009-05-19
申请号：US11191900
申请日：2005-07-27
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/004 , G11C2213/31 , G11C2213/77 , G11C2213/79
摘要： A nonvolatile semiconductor memory device according to the present invention comprises a memory cell selecting circuit for selecting the memory cell from the memory cell array in units of row, column or memory cell; a read voltage application circuit for applying a read voltage to the variable resistor element of the selected memory cells selected by the memory cell selecting circuit; and a read circuit for detecting the amount of the read current flowing in accordance with the resistance value of the variable resistor element with respect to the memory cell to be read of the selected memory cells and reading the information stored in the memory cell to be read; and the read voltage application circuit applies a dummy read voltage having reversed polarity from the read voltage to the variable resistor element of the selected memory cell.
摘要翻译： 根据本发明的非易失性半导体存储器件包括存储单元选择电路，用于以行，列或存储单元为单位从存储单元阵列中选择存储单元; 读取电压施加电路，用于对由存储单元选择电路选择的所选存储单元的可变电阻元件施加读取电压; 以及读取电路，用于根据可变电阻器元件的电阻值相对于要选择的存储器单元读取的存储单元检测流过的读取电流的量并读取存储在待读取的存储器单元中的信息 ; 并且读取电压施加电路将具有与读取电压相反的极性的虚拟读取电压施加到所选存储单元的可变电阻器元件。
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公开(公告)号：US07016094B2
公开(公告)日：2006-03-21
申请号：US10755637
申请日：2004-01-12
申请人： Nobuyoshi Awaya , David R. Evans
发明人： Nobuyoshi Awaya , David R. Evans
CPC分类号： G02F1/0316 , G02F1/05 , G02F1/225 , G02F1/3132
摘要： Perovskite materials having magnetoresistive effect under the influence of an electric field can be employed in the construction of nonvolatile solid state electro-optic modulator. These materials display nonvolatile changes in electrical resistance and reactant when subjected to an electric field. As with other known perovskite materials, this is accompanied by nonvolatile changes in electro-optic properties related to dispersion and absorption of electromagnetic radiation. The nonvolatility of these materials is exploited in the construction of nonvolatile display and nonvolatile solid state electro-optic modulators such as waveguide switch or phase or amplitude modulators.
摘要翻译： 在电场影响下具有磁阻效应的钙钛矿材料可用于构建非挥发性固态电光调制器。 这些材料在经受电场时显示电阻和反应物的非挥发性变化。 与其他已知的钙钛矿材料一样，伴随着与电磁辐射的分散和吸收相关的电光性质的不稳定变化。 这些材料的非易失性被用于构建非易失性显示器和非挥发性固态电光调制器，例如波导开关或相位或振幅调制器。
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公开(公告)号：US20060023497A1
公开(公告)日：2006-02-02
申请号：US11191900
申请日：2005-07-27
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/004 , G11C2213/31 , G11C2213/77 , G11C2213/79
摘要： A nonvolatile semiconductor memory device according to the present invention comprises a memory cell selecting circuit for selecting the memory cell from the memory cell array in units of row, column or memory cell; a read voltage application circuit for applying a read voltage to the variable resistor element of the selected memory cells selected by the memory cell selecting circuit; and a read circuit for detecting the amount of the read current flowing in accordance with the resistance value of the variable resistor element with respect to the memory cell to be read of the selected memory cells and reading the information stored in the memory cell to be read; and the read voltage application circuit applies a dummy read voltage having reversed polarity from the read voltage to the variable resistor element of the selected memory cell.
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公开(公告)号：US20050145910A1
公开(公告)日：2005-07-07
申请号：US11001744
申请日：2004-12-01
申请人： Yukio Tamai , Nobuyoshi Awaya , Shinji Kobayashi , Hidechika Kawazoe , Toshimasa Suzuki , Hidetoshi Masuda , Naoto Hagiwara , Yuji Matsushita , Yuji Nishi
发明人： Yukio Tamai , Nobuyoshi Awaya , Shinji Kobayashi , Hidechika Kawazoe , Toshimasa Suzuki , Hidetoshi Masuda , Naoto Hagiwara , Yuji Matsushita , Yuji Nishi
IPC分类号： H01L27/10 , G11C13/00 , H01L21/8234 , H01L29/76 , H01L45/00
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/52 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625
摘要： In a nonvolatile semiconductor memory device including a variable resistive element formed by sequentially stacking a lower electrode, a variable resistor with a perovskite-type crystal structure, and an upper electrode, at least one of the lower electrode and the upper electrode is a particulate electrode configured to include a particulate conductor aggregate, so that the contact area with the variable resistor at an interface is effectively reduced to realize high initial resistance of the variable resistive element. Further, a film of the variable resistor is preferably formed so as to be in a highly crystalline state.
摘要翻译： 在包括通过顺序堆叠下电极，具有钙钛矿型晶体结构的可变电阻器和上电极形成的可变电阻元件的非易失性半导体存储器件中，下电极和上电极中的至少一个是颗粒电极 被配置为包括颗粒状导体集合体，使得与界面处的可变电阻器的接触面积被有效地减小以实现可变电阻元件的高初始电阻。 此外，可变电阻器的膜优选形成为高度结晶的状态。
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公开(公告)号：US06630740B1
公开(公告)日：2003-10-07
申请号：US09671737
申请日：2000-09-29
申请人： Kunihiko Orita , Nobuyoshi Awaya
发明人： Kunihiko Orita , Nobuyoshi Awaya
IPC分类号： H01L2940
CPC分类号： H01L23/5329 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interlayer insulating film having a connection hole and a line insulating film having a wiring groove are formed on a semiconductor substrate. The interlayer insulating film and the line insulating film are made principally of SiO2, and contain phosphorus and hydrocarbon. A copper wiring film that covers the connection hole and the wiring groove of the interlayer insulating film and the line insulating film is formed. Therefore, this semiconductor device is able to prevent the diffusion of copper into a low dielectric constant insulating film constructed of the interlayer insulating film and the line insulating film, reduce the dielectric constant and water absorptively of the low dielectric constant insulating film and reduce the cross-talk noises.
摘要翻译： 在半导体基板上形成具有连接孔的层间绝缘膜和具有布线槽的线绝缘膜。 层间绝缘膜和线绝缘膜主要由SiO 2制成，并含有磷和烃。 形成覆盖层间绝缘膜的连接孔和布线槽的铜布线膜和线绝缘膜。 因此，该半导体装置能够防止铜扩散到由层间绝缘膜和线绝缘膜构成的低介电常数绝缘膜中，降低介电常数并吸收低介电常数绝缘膜并减少交叉 -talk的噪音。
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