公开(公告)号：US10797142B2

公开(公告)日：2020-10-06

申请号：US16208288

申请日：2018-12-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Nhan Do

IPC: H01L29/423 ,  H01L27/11521 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L21/027 ,  H01L21/308 ,  H01L21/3105 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: A memory cell is formed on a semiconductor substrate having an upper surface with a plurality of upwardly extending fins. First and second fins extend in one direction, and a third fin extends in an orthogonal direction. Spaced apart source and drain regions are formed in each of the first and second fins, defining a channel region extending there between in each of the first and second fins. The source regions are disposed at intersections between the third fin and the first and second fins. A floating gate is disposed laterally between the first and second fins, and laterally adjacent to the third fin, and extends along first portions of the channel regions. A word line gate extends along second portions of the channel regions. A control gate is disposed over the floating gate. An erase gate is disposed over the source regions and the floating gate.

公开(公告)号：US10790292B2

公开(公告)日：2020-09-29

申请号：US16057749

申请日：2018-08-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Xian Liu ,  Feng Zhou ,  Parviz Ghazavi ,  Steven Lemke ,  Nhan Do

IPC: H01L27/11521 ,  H01L21/027 ,  H01L27/11536 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/08 ,  H01L29/423 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/265 ,  H01L21/321

Abstract: A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate. The memory cell stacks, select gate poly, and source regions for the memory devices are formed in the memory area before the logic devices are formed in the logic areas. The various oxide, nitride and poly layers used to form the gate stacks in the memory area are formed in the logic areas as well. Only after the memory cell stacks and select gate poly are formed, and the memory area protected by one or more protective layers, are the oxide, nitride and poly layers used to form the memory cell stacks removed from the logic areas, and the logic devices are then formed.

公开(公告)号：US10741568B2

公开(公告)日：2020-08-11

申请号：US16231231

申请日：2018-12-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G06N3/04 ,  G06F3/06 ,  H01L27/115 ,  H01L29/788 ,  H01L27/11531 ,  G06N3/08 ,  G11C16/04

Abstract: Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

公开(公告)号：US20200233482A1

公开(公告)日：2020-07-23

申请号：US16354040

申请日：2019-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten ,  Nhan Do

IPC: G06F1/3234 ,  G11C16/04 ,  G11C11/54 ,  G06F17/16 ,  G06N3/08

Abstract: Numerous embodiments of power management techniques are disclosed for various operations involving one or more vector-by-matrix multiplication (VMM) arrays within an artificial neural network.

公开(公告)号：US10714634B2

公开(公告)日：2020-07-14

申请号：US16166342

申请日：2018-10-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Chien-Sheng Su ,  Nhan Do

IPC: H01L29/788 ,  H01L27/11521 ,  H01L29/49 ,  H01L27/11529 ,  H01L27/11546 ,  H01L27/11524 ,  H01L27/11534 ,  H01L21/28

Abstract: A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate. Portions of the upper surface of the substrate under the memory cell and the high voltage device are recessed relative to the upper surface portion of the substrate under the logic device. The memory cell includes a polysilicon floating gate disposed over a first portion of a channel region of the substrate, a polysilicon word line gate disposed over a second portion of the channel region, a polysilicon erase gate disposed over a source region of the substrate, and a metal control gate disposed over the floating gate and insulated from the floating gate by a composite insulation layer that includes a high-K dielectric. The logic device includes a metal gate disposed over the substrate. The high voltage device includes a polysilicon gate disposed over the substrate.

公开(公告)号：US10600794B2

公开(公告)日：2020-03-24

申请号：US16160812

申请日：2018-10-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Andy Liu ,  Xian Liu ,  Leo Xing ,  Melvin Diao ,  Nhan Do

IPC: H01L29/66 ,  H01L29/788 ,  H01L29/423 ,  H01L27/11521 ,  H01L27/11524 ,  H01L21/28

Abstract: A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate. An erase gate, or a pair of erase gates, are disposed over and insulated from the floating gates, respectively. A word line gate is disposed over and insulated from a portion of the upper surface that is between the first and second trenches. A first source region is formed in the substrate under the first trench, and a second source region formed in the substrate under the second trench. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.

公开(公告)号：US10586598B2

公开(公告)日：2020-03-10

申请号：US16025039

申请日：2018-07-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Vipin Tiwari ,  Nhan Do

IPC: G11C16/06 ,  G11C16/10 ,  G11C16/28

Abstract: A memory device that includes a plurality of memory cells arranged in rows and columns, a plurality of bit lines each connected to one of the columns of memory cells, and a plurality of differential sense amplifiers each having first and second inputs and an output. For each of the differential sense amplifiers, the differential sense amplifier is configured to generate an output signal on the output having an amplitude that is based upon a difference in signal amplitudes on the first and second inputs, the first input is connected to one of the bit lines, and the second input is connected to another one of the bit lines. Alternately, one or more sense amplifiers are configured to detect signal amplitudes on the bit lines, and the device includes calculation circuitry configured to produce output signals each based upon a difference in signal amplitudes on two of the bit lines.

公开(公告)号：US10580492B2

公开(公告)日：2020-03-03

申请号：US16107282

申请日：2018-08-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  H01L27/11521 ,  H01L27/11524 ,  G06N3/06 ,  G06N3/063 ,  G11C16/24

Abstract: A memory array with memory cells arranged in rows and columns. Each memory cell includes source and drain regions with a channel region there between, a floating gate disposed over a first channel region portion, and a second gate disposed over a second channel region portion. A plurality of bit lines each extends along one of the columns and is electrically connected to the drain regions of a first group of one or more of the memory cells in the column and is electrically isolated from the drain regions of a second group of one or more of the memory cells in the column. A plurality of source lines each is electrically connected to the source regions of the memory cells in one of the columns or rows. A plurality of gate lines each is electrically connected to the second gates of memory cells in one of the columns or rows.

公开(公告)号：US20200066738A1

公开(公告)日：2020-02-27

申请号：US16209515

申请日：2018-12-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Yuri Tkachev ,  Alexander Kotov ,  Nhan Do

IPC: H01L27/11521 ,  H01L29/788 ,  G11C16/04

Abstract: A memory device with a memory cell and control circuitry. The memory cell includes source and drain regions formed in a semiconductor substrate, with a channel region extending there between. A floating gate is disposed over a first portion of the channel region for controlling its conductivity. A select gate is disposed over a second portion of the channel region for controlling its conductivity. A control gate is disposed over the floating gate. An erase gate is disposed over the source region and adjacent to the floating gate. The control circuitry is configured to perform a program operation by applying a negative voltage to the erase gate for causing electrons to tunnel from the erase gate to the floating gate, and perform an erase operation by applying a positive voltage to the erase gate for causing electrons to tunnel from the floating gate to the erase gate.

公开(公告)号：US20200035310A1

公开(公告)日：2020-01-30

申请号：US16590798

申请日：2019-10-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/34 ,  G11C11/54 ,  G11C16/04 ,  G06N3/08 ,  G11C16/30 ,  G11C16/26

Abstract: Numerous embodiments of a data refresh method and apparatus for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Various embodiments of a data drift detector suitable for detecting data drift in flash memory cells within the VMM array are disclosed.