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    Fin field effect transistor and method of fabricating the same
    21.
    发明申请
    Fin field effect transistor and method of fabricating the same 有权
    Fin场效应晶体管及其制造方法

    公开(公告)号：US20100109057A1

    公开(公告)日：2010-05-06

    申请号：US12459660

    申请日：2009-07-06

    申请人： Jong-hoon Kang ,  Tai-su Park ,  Dong-chan Kim ,  Yu-gyun Shin ,  Jeong-do Ryu ,  Seong-hoon Jeong

    发明人： Jong-hoon Kang ,  Tai-su Park ,  Dong-chan Kim ,  Yu-gyun Shin ,  Jeong-do Ryu ,  Seong-hoon Jeong

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7854 ,  H01L29/66795

    摘要： A fin field effect transistor includes a fin protruding from a semiconductor substrate, a gate insulating layer formed so as to cover upper and lateral surfaces of the fin, and a gate electrode formed across the fin so as to cover the gate insulating layer. An upper edge of the fin is rounded so that an electric field concentratedly applied to the upper edge of the fin through the gate electrode is dispersed. A thickness of a portion of the gate insulating layer formed on an upper surface of the fin is greater than a thickness of a portion of the gate insulating layer formed on a lateral surface of the fin, in order to reduce an electric field applied through the gate electrode.

    摘要翻译： 翅片场效应晶体管包括从半导体衬底突出的鳍片，形成为覆盖鳍片的上表面和侧表面的栅极绝缘层，以及跨过鳍状物形成以覆盖栅极绝缘层的栅电极。 鳍的上边缘是圆形的，使得通过栅电极集中地施加到鳍的上边缘的电场被分散。 形成在鳍的上表面上的栅极绝缘层的一部分的厚度大于形成在鳍的侧表面上的栅极绝缘层的一部分的厚度，以便减少通过 栅电极。

    Method of fabricating semiconductor device having dual gate
    23.
    发明授权
    Method of fabricating semiconductor device having dual gate 有权
    制造具有双栅极的半导体器件的方法

    公开(公告)号：US08932922B2

    公开(公告)日：2015-01-13

    申请号：US13116045

    申请日：2011-05-26

    申请人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

    发明人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

    IPC分类号： H01L21/8238 ,  H01L29/51 ,  H01L21/28

    CPC分类号： H01L21/823828 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518

    摘要： A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.

    摘要翻译： 制造具有双栅极的半导体器件的方法允许栅极具有各种阈值电压。 该方法包括：跨越衬底上的第一区域和第二区域以上述顺序形成栅极绝缘层，第一覆盖层和阻挡层，通过去除第一覆盖层和暴露第一区域上的栅极绝缘层; 所述阻挡层从所述第一区域形成在所述第一区域中的所述栅极绝缘层上和所述第二区域中的所述势垒层上形成第二覆盖层，并对形成有所述第二覆盖层的所述基板进行热处理。 热处理使得第二覆盖层的材料扩散到第一区域中的栅极绝缘层中，并且第一覆盖层的材料扩散到第二区域中的栅极绝缘层中。 因此，可以在第一和第二区域中形成具有不同阈值电压的器件。

    Methods of forming semiconductor devices having gates with different work functions using selective injection of diffusion inhibiting materials
    24.
    发明授权
    Methods of forming semiconductor devices having gates with different work functions using selective injection of diffusion inhibiting materials 有权
    使用选择性注入扩散抑制材料形成具有不同功函数的栅极的半导体器件的方法

    公开(公告)号：US08293599B2

    公开(公告)日：2012-10-23

    申请号：US12540090

    申请日：2009-08-12

    申请人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

    发明人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L21/823842

    摘要： A semiconductor device that has a dual gate having different work functions is simply formed by using a selective nitridation. A gate insulating layer is formed on a semiconductor substrate including a first region and a second region, on which devices having different threshold voltages are to be formed. A diffusion inhibiting material is selectively injected into the gate insulating layer in one of the first region and the second region. A diffusion layer is formed on the gate insulating layer. A work function controlling material is directly diffused from the diffusion layer to the gate insulating layer using a heat treatment, wherein the gate insulting layer is self-aligned capped with the selectively injected diffusion inhibiting material so that the work function controlling material is diffused into the other of the first region and the second region. The gate insulating layer is entirely exposed by removing the diffusion layer. A gate electrode layer is formed on the exposed gate insulating layer. A first gate and a second gate having different work functions are respectively formed in the first region and the second region by etching the gate electrode layer and the gate insulating layer.

    摘要翻译： 具有不同工作功能的双栅极的半导体器件通过使用选择性氮化简单地形成。 在包括第一区域和第二区域的半导体衬底上形成栅极绝缘层，在其上形成具有不同阈值电压的器件。 扩散抑制材料被选择性地注入到第一区域和第二区域之一中的栅极绝缘层中。 在栅极绝缘层上形成扩散层。 工作功能控制材料通过热处理从扩散层直接扩散到栅极绝缘层，其中栅极绝缘层由选择性注入的扩散抑制材料自对准封盖，使得功函数控制材料扩散到 第一个地区和第二个地区的其他地区。 通过去除扩散层，完全暴露栅极绝缘层。 在暴露的栅极绝缘层上形成栅极电极层。 通过蚀刻栅极电极层和栅极绝缘层，分别在第一区域和第二区域中形成具有不同功函数的第一栅极和第二栅极。

    Method of manufacturing semiconductor device
    26.
    发明申请
    Method of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20100330758A1

    公开(公告)日：2010-12-30

    申请号：US12656130

    申请日：2010-01-19

    申请人： Jin-bum Kim ,  Wook-je Kim ,  Kwan-heum Lee ,  Yu-gyun Shin ,  Sun-ghil Lee

    发明人： Jin-bum Kim ,  Wook-je Kim ,  Kwan-heum Lee ,  Yu-gyun Shin ,  Sun-ghil Lee

    IPC分类号： H01L21/8242 ,  H01L21/283

    CPC分类号： H01L21/7687 ,  H01L27/10855 ,  H01L28/91

    摘要： A method of manufacturing a semiconductor device may include forming a first interlayer insulation layer on a substrate including at least one gate structure formed thereon, the substrate having a plurality of source/drain regions formed on both sides of the at least one gate structure, forming at least one buried contact plug on at least one of the plurality of source/drain regions and in the first interlayer insulation layer, forming a second interlayer insulation layer on the first interlayer insulation layer and the at least one buried contact plug, exposing the at least one buried contact plug in the second interlayer insulation layer by forming at least one contact hole, implanting ions in the at least one contact hole in order to create an amorphous upper portion of the at least one buried contact plug, depositing a lower electrode layer on the second interlayer insulation layer and the at least one contact hole, and forming a metal silicide layer in the amorphous upper portion of the at least one buried contact plug.

    摘要翻译： 制造半导体器件的方法可以包括在包括形成在其上的至少一个栅极结构的衬底上形成第一层间绝缘层，所述衬底具有形成在所述至少一个栅极结构的两侧上的多个源/漏区，形成 在所述多个源极/漏极区域和所述第一层间绝缘层中的至少一个上的至少一个埋置的接触插塞，在所述第一层间绝缘层和所述至少一个埋置的接触插塞上形成第二层间绝缘层， 通过形成至少一个接触孔，在所述至少一个接触孔中注入离子，以形成所述至少一个埋入接触插塞的非晶体上部，沉积下部电极层 在所述第二层间绝缘层和所述至少一个接触孔上，并且在所述非晶体上部形成金属硅化物层 的所述至少一个埋入式接触插塞。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING DUAL GATE
    27.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING DUAL GATE 有权
    制造具有双门的半导体器件的方法

    公开(公告)号：US20100203716A1

    公开(公告)日：2010-08-12

    申请号：US12580302

    申请日：2009-10-16

    申请人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

    发明人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

    IPC分类号： H01L21/28 ,  H01L21/336

    CPC分类号： H01L21/823828 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518

    摘要： A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.

    摘要翻译： 制造具有双栅极的半导体器件的方法允许栅极具有各种阈值电压。 该方法包括：跨越衬底上的第一区域和第二区域以上述顺序形成栅极绝缘层，第一覆盖层和阻挡层，通过去除第一覆盖层和暴露第一区域上的栅极绝缘层; 所述阻挡层从所述第一区域形成在所述第一区域中的所述栅极绝缘层上和所述第二区域中的所述势垒层上形成第二覆盖层，并对形成有所述第二覆盖层的所述基板进行热处理。 热处理使得第二覆盖层的材料扩散到第一区域中的栅极绝缘层中，并且第一覆盖层的材料扩散到第二区域中的栅极绝缘层中。 因此，可以在第一和第二区域中形成具有不同阈值电压的器件。

    Methods of forming trench-based isolation regions with reduced susceptibility to edge defects
    28.
    发明授权
    Methods of forming trench-based isolation regions with reduced susceptibility to edge defects 失效
    形成具有降低的边缘缺陷敏感性的基于沟槽的隔离区域的方法

    公开(公告)号：US5885883A

    公开(公告)日：1999-03-23

    申请号：US834245

    申请日：1997-04-15

    申请人： Moon-han Park ,  Yu-gyun Shin

    发明人： Moon-han Park ,  Yu-gyun Shin

    IPC分类号： H01L21/76 ,  H01L21/762

    CPC分类号： H01L21/76232

    摘要： Methods of forming trench-based isolation regions with reduced susceptibility to edge defects include the steps of forming trenches at a face of a semiconductor substrate and then filling the trenches with electrically insulating regions. However, to prevent exposure of those portions of the substrate extending adjacent the trenches, supplemental oxide regions are formed at the interfaces between the upper portions of the trench sidewalls and the electrically insulating regions in the trenches, by exposing the electrically insulating regions to an oxidation atmosphere at a temperature in a range between about 950.degree. C. and 1100.degree. C. In particular, the supplemental oxide regions are formed as thermal oxides of higher density than the electrically insulating regions in the trenches. Thus, the supplemental oxide regions are more resistant to chemical etchants. Accordingly, when the electrically insulating regions are planarized and etched during back end processing steps, the supplemental oxide regions will not be entirely etched and, therefore, those portions of the substrate (i.e., active regions) extending adjacent the trenches will not be exposed.

    摘要翻译： 形成具有降低的边缘缺陷敏感性的沟槽隔离区的方法包括以下步骤：在半导体衬底的表面形成沟槽，然后用电绝缘区填充沟槽。 然而，为了防止邻近沟槽延伸的衬底的那些部分的暴露，在沟槽侧壁的上部和沟槽中的电绝缘区域之间的界面处，通过​​将电绝缘区域暴露于氧化物形成辅助氧化物区域 在约950℃至1100℃的温度范围内的气氛。特别地，补充氧化物区域形成为比沟槽中的电绝缘区域更高密度的热氧化物。 因此，补充氧化物区域更耐化学蚀刻剂。 因此，当在后端处理步骤中对电绝缘区域进行平面化和蚀刻时，补充氧化物区域将不会被完全蚀刻，因此，邻近沟槽延伸的衬底（即，有源区域）的那些部分将不被暴露。